Not your father's timing anymore - Novel approaches to timing of digital circuits

Ulf Schlichtmann

doi:10.1109/CSTIC.2019.8755618

Not your father's timing anymore - Novel approaches to timing of digital circuits

Ulf Schlichtmann

Chair of Electronic Design Automation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In traditional digital circuits, flip-flops are used as memory components for state machines and synchronization components to implement pipelining. The clock frequency of a circuit is determined by the longest combinational path between flip-flops. To improve circuit performance, combinational logic blocks between flip-flops have been the focus of optimization, with techniques such as sizing and retiming. However, the ever-increasing challenges from factors such as variations and aging have made further increase of circuit performance extremely difficult. In this paper, timing of digital circuits is examined and a new concept to introduce wave-pipelining into sequential design is presented. Two application scenarios of this concept, VirtualSync and TimingCamouflage, are presented to demonstrate the potential of this concept in improving circuit performance and netlist security, respectively.

Original language	English
Title of host publication	China Semiconductor Technology International Conference 2019, CSTIC 2019
Editors	Cor Claeys, Ru Huang, Hanming Wu, Qinghuang Lin, Steve Liang, Peilin Song, Zhen Guo, Kafai Lai, Ying Zhang, Xinping Qu, Hsiang-Lan Lung, Wenjian Yu
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538674437
DOIs	https://doi.org/10.1109/CSTIC.2019.8755618
State	Published - Mar 2019
Event	2019 China Semiconductor Technology International Conference, CSTIC 2019 - Shanghai, China Duration: 18 Mar 2019 → 19 Mar 2019

Publication series

Name	China Semiconductor Technology International Conference 2019, CSTIC 2019

Conference

Conference	2019 China Semiconductor Technology International Conference, CSTIC 2019
Country/Territory	China
City	Shanghai
Period	18/03/19 → 19/03/19

Access to Document

10.1109/CSTIC.2019.8755618

Cite this

Schlichtmann, U. (2019). Not your father's timing anymore - Novel approaches to timing of digital circuits. In C. Claeys, R. Huang, H. Wu, Q. Lin, S. Liang, P. Song, Z. Guo, K. Lai, Y. Zhang, X. Qu, H.-L. Lung, & W. Yu (Eds.), China Semiconductor Technology International Conference 2019, CSTIC 2019 Article 8755618 (China Semiconductor Technology International Conference 2019, CSTIC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSTIC.2019.8755618

Schlichtmann, Ulf. / Not your father's timing anymore - Novel approaches to timing of digital circuits. China Semiconductor Technology International Conference 2019, CSTIC 2019. editor / Cor Claeys ; Ru Huang ; Hanming Wu ; Qinghuang Lin ; Steve Liang ; Peilin Song ; Zhen Guo ; Kafai Lai ; Ying Zhang ; Xinping Qu ; Hsiang-Lan Lung ; Wenjian Yu. Institute of Electrical and Electronics Engineers Inc., 2019. (China Semiconductor Technology International Conference 2019, CSTIC 2019).

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title = "Not your father's timing anymore - Novel approaches to timing of digital circuits",

abstract = "In traditional digital circuits, flip-flops are used as memory components for state machines and synchronization components to implement pipelining. The clock frequency of a circuit is determined by the longest combinational path between flip-flops. To improve circuit performance, combinational logic blocks between flip-flops have been the focus of optimization, with techniques such as sizing and retiming. However, the ever-increasing challenges from factors such as variations and aging have made further increase of circuit performance extremely difficult. In this paper, timing of digital circuits is examined and a new concept to introduce wave-pipelining into sequential design is presented. Two application scenarios of this concept, VirtualSync and TimingCamouflage, are presented to demonstrate the potential of this concept in improving circuit performance and netlist security, respectively.",

author = "Ulf Schlichtmann",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 China Semiconductor Technology International Conference, CSTIC 2019 ; Conference date: 18-03-2019 Through 19-03-2019",

year = "2019",

month = mar,

doi = "10.1109/CSTIC.2019.8755618",

language = "English",

series = "China Semiconductor Technology International Conference 2019, CSTIC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Cor Claeys and Ru Huang and Hanming Wu and Qinghuang Lin and Steve Liang and Peilin Song and Zhen Guo and Kafai Lai and Ying Zhang and Xinping Qu and Hsiang-Lan Lung and Wenjian Yu",

booktitle = "China Semiconductor Technology International Conference 2019, CSTIC 2019",

}

Schlichtmann, U 2019, Not your father's timing anymore - Novel approaches to timing of digital circuits. in C Claeys, R Huang, H Wu, Q Lin, S Liang, P Song, Z Guo, K Lai, Y Zhang, X Qu, H-L Lung & W Yu (eds), China Semiconductor Technology International Conference 2019, CSTIC 2019., 8755618, China Semiconductor Technology International Conference 2019, CSTIC 2019, Institute of Electrical and Electronics Engineers Inc., 2019 China Semiconductor Technology International Conference, CSTIC 2019, Shanghai, China, 18/03/19. https://doi.org/10.1109/CSTIC.2019.8755618

Not your father's timing anymore - Novel approaches to timing of digital circuits. / Schlichtmann, Ulf.
China Semiconductor Technology International Conference 2019, CSTIC 2019. ed. / Cor Claeys; Ru Huang; Hanming Wu; Qinghuang Lin; Steve Liang; Peilin Song; Zhen Guo; Kafai Lai; Ying Zhang; Xinping Qu; Hsiang-Lan Lung; Wenjian Yu. Institute of Electrical and Electronics Engineers Inc., 2019. 8755618 (China Semiconductor Technology International Conference 2019, CSTIC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Not your father's timing anymore - Novel approaches to timing of digital circuits

AU - Schlichtmann, Ulf

PY - 2019/3

Y1 - 2019/3

N2 - In traditional digital circuits, flip-flops are used as memory components for state machines and synchronization components to implement pipelining. The clock frequency of a circuit is determined by the longest combinational path between flip-flops. To improve circuit performance, combinational logic blocks between flip-flops have been the focus of optimization, with techniques such as sizing and retiming. However, the ever-increasing challenges from factors such as variations and aging have made further increase of circuit performance extremely difficult. In this paper, timing of digital circuits is examined and a new concept to introduce wave-pipelining into sequential design is presented. Two application scenarios of this concept, VirtualSync and TimingCamouflage, are presented to demonstrate the potential of this concept in improving circuit performance and netlist security, respectively.

AB - In traditional digital circuits, flip-flops are used as memory components for state machines and synchronization components to implement pipelining. The clock frequency of a circuit is determined by the longest combinational path between flip-flops. To improve circuit performance, combinational logic blocks between flip-flops have been the focus of optimization, with techniques such as sizing and retiming. However, the ever-increasing challenges from factors such as variations and aging have made further increase of circuit performance extremely difficult. In this paper, timing of digital circuits is examined and a new concept to introduce wave-pipelining into sequential design is presented. Two application scenarios of this concept, VirtualSync and TimingCamouflage, are presented to demonstrate the potential of this concept in improving circuit performance and netlist security, respectively.

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U2 - 10.1109/CSTIC.2019.8755618

DO - 10.1109/CSTIC.2019.8755618

M3 - Conference contribution

AN - SCOPUS:85069470916

T3 - China Semiconductor Technology International Conference 2019, CSTIC 2019

BT - China Semiconductor Technology International Conference 2019, CSTIC 2019

A2 - Claeys, Cor

A2 - Huang, Ru

A2 - Wu, Hanming

A2 - Lin, Qinghuang

A2 - Liang, Steve

A2 - Song, Peilin

A2 - Guo, Zhen

A2 - Lai, Kafai

A2 - Zhang, Ying

A2 - Qu, Xinping

A2 - Lung, Hsiang-Lan

A2 - Yu, Wenjian

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 China Semiconductor Technology International Conference, CSTIC 2019

Y2 - 18 March 2019 through 19 March 2019

ER -

Schlichtmann U. Not your father's timing anymore - Novel approaches to timing of digital circuits. In Claeys C, Huang R, Wu H, Lin Q, Liang S, Song P, Guo Z, Lai K, Zhang Y, Qu X, Lung HL, Yu W, editors, China Semiconductor Technology International Conference 2019, CSTIC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8755618. (China Semiconductor Technology International Conference 2019, CSTIC 2019). doi: 10.1109/CSTIC.2019.8755618

Not your father's timing anymore - Novel approaches to timing of digital circuits

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