No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits

Ann Christin Bette; Robin Falter; Matthias Ludwig; Bernhard Lippmann; Frank Siegelin; Peter Egger; Alois Knoll

doi:10.1109/IPFA58228.2023.10249049

No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits

Ann Christin Bette, Robin Falter, Matthias Ludwig, Bernhard Lippmann, Frank Siegelin, Peter Egger, Alois Knoll

nformatics 6 - Chair of IRobotics, Artificial Intelligence and Real-time Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Acquiring images of the layout of integrated circuits increases the demands on electron microscopy as the technology scaling continues. Each new chip generation makes producing stable and processable image quality more difficult. Currently, no automated, technology-agnostic solution supports the human operator in creating optimal layout images. Therefore, we propose an image quality assessment framework that determines the optimal microscope settings for each technology sample. We define the optimal settings as the minimum possible scan time, which still maintains the processability of the acquired images. The two implemented machine learning algorithms do not require a noise and distortion-free reference image. We compare both models on an updated version of the REFICS dataset and investigate their behavior for different noise types. Finally, we use our framework to fully recover the layout of a 28nm technology, reducing scan time by more than 95%.

Original language	English
Title of host publication	2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350301649
DOIs	https://doi.org/10.1109/IPFA58228.2023.10249049
State	Published - 2023
Event	2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023 - Pulau Pinang, Malaysia Duration: 24 Jul 2023 → 27 Jul 2023

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume	2023-July

Conference

Conference	2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023
Country/Territory	Malaysia
City	Pulau Pinang
Period	24/07/23 → 27/07/23

Keywords

IC image analysis
IC reverse engineering
Layout validation
No-reference image quality assessment
Physical inspection
SEM imaging

Access to Document

10.1109/IPFA58228.2023.10249049

Cite this

Bette, A. C., Falter, R., Ludwig, M., Lippmann, B., Siegelin, F., Egger, P., & Knoll, A. (2023). No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits. In 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2023-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA58228.2023.10249049

Bette, Ann Christin ; Falter, Robin ; Ludwig, Matthias et al. / No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits. 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{b788cdc2975d4a67bd06de1a2d95be7c,

title = "No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits",

abstract = "Acquiring images of the layout of integrated circuits increases the demands on electron microscopy as the technology scaling continues. Each new chip generation makes producing stable and processable image quality more difficult. Currently, no automated, technology-agnostic solution supports the human operator in creating optimal layout images. Therefore, we propose an image quality assessment framework that determines the optimal microscope settings for each technology sample. We define the optimal settings as the minimum possible scan time, which still maintains the processability of the acquired images. The two implemented machine learning algorithms do not require a noise and distortion-free reference image. We compare both models on an updated version of the REFICS dataset and investigate their behavior for different noise types. Finally, we use our framework to fully recover the layout of a 28nm technology, reducing scan time by more than 95\%.",

keywords = "IC image analysis, IC reverse engineering, Layout validation, No-reference image quality assessment, Physical inspection, SEM imaging",

author = "Bette, \{Ann Christin\} and Robin Falter and Matthias Ludwig and Bernhard Lippmann and Frank Siegelin and Peter Egger and Alois Knoll",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023 ; Conference date: 24-07-2023 Through 27-07-2023",

year = "2023",

doi = "10.1109/IPFA58228.2023.10249049",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023",

}

Bette, AC, Falter, R, Ludwig, M, Lippmann, B, Siegelin, F, Egger, P & Knoll, A 2023, No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits. in 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023. Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, vol. 2023-July, Institute of Electrical and Electronics Engineers Inc., 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023, Pulau Pinang, Malaysia, 24/07/23. https://doi.org/10.1109/IPFA58228.2023.10249049

No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits. / Bette, Ann Christin; Falter, Robin; Ludwig, Matthias et al.
2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2023-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits

AU - Bette, Ann Christin

AU - Falter, Robin

AU - Ludwig, Matthias

AU - Lippmann, Bernhard

AU - Siegelin, Frank

AU - Egger, Peter

AU - Knoll, Alois

PY - 2023

Y1 - 2023

N2 - Acquiring images of the layout of integrated circuits increases the demands on electron microscopy as the technology scaling continues. Each new chip generation makes producing stable and processable image quality more difficult. Currently, no automated, technology-agnostic solution supports the human operator in creating optimal layout images. Therefore, we propose an image quality assessment framework that determines the optimal microscope settings for each technology sample. We define the optimal settings as the minimum possible scan time, which still maintains the processability of the acquired images. The two implemented machine learning algorithms do not require a noise and distortion-free reference image. We compare both models on an updated version of the REFICS dataset and investigate their behavior for different noise types. Finally, we use our framework to fully recover the layout of a 28nm technology, reducing scan time by more than 95%.

AB - Acquiring images of the layout of integrated circuits increases the demands on electron microscopy as the technology scaling continues. Each new chip generation makes producing stable and processable image quality more difficult. Currently, no automated, technology-agnostic solution supports the human operator in creating optimal layout images. Therefore, we propose an image quality assessment framework that determines the optimal microscope settings for each technology sample. We define the optimal settings as the minimum possible scan time, which still maintains the processability of the acquired images. The two implemented machine learning algorithms do not require a noise and distortion-free reference image. We compare both models on an updated version of the REFICS dataset and investigate their behavior for different noise types. Finally, we use our framework to fully recover the layout of a 28nm technology, reducing scan time by more than 95%.

KW - IC image analysis

KW - IC reverse engineering

KW - Layout validation

KW - No-reference image quality assessment

KW - Physical inspection

KW - SEM imaging

UR - http://www.scopus.com/inward/record.url?scp=85173558360&partnerID=8YFLogxK

U2 - 10.1109/IPFA58228.2023.10249049

DO - 10.1109/IPFA58228.2023.10249049

M3 - Conference contribution

AN - SCOPUS:85173558360

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

BT - 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023

Y2 - 24 July 2023 through 27 July 2023

ER -

Bette AC, Falter R, Ludwig M, Lippmann B, Siegelin F, Egger P et al. No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits. In 2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA58228.2023.10249049

No-Reference Image Quality Assessment for Reverse Engineering of Integrated Circuits

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