Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing

Emilio Perez Bosch Quesada, Tommaso Rizzi, Aditya Gupta, Mamathamba K. Mahadevaiah, Andreas Schubert, Stefan Pechmann, Ruolan Jia, Max Uhlmann, Amelie Hagelauer, Christian Wenger, Eduardo Perez

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.

Original languageEnglish
Title of host publication14th Spanish Conference on Electron Devices, CDE 2023 - Proceedings
EditorsE. Maset, C. Reig
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350302400
DOIs
StatePublished - 2023
Event14th Spanish Conference on Electron Devices, CDE 2023 - Valencia, Spain
Duration: 6 Jun 20238 Jun 2023

Publication series

Name14th Spanish Conference on Electron Devices, CDE 2023 - Proceedings

Conference

Conference14th Spanish Conference on Electron Devices, CDE 2023
Country/TerritorySpain
CityValencia
Period6/06/238/06/23

Keywords

  • Enclosed Layout Transistor
  • hardness-by-design
  • in-memory computing
  • memristive devices
  • radiation-hard

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