TY - GEN
T1 - MuDSE
T2 - 2024 IEEE International Conference on Omni-Layer Intelligent Systems, COINS 2024
AU - Hoffman, Alexander
AU - Fnayou, Ala
AU - Smirnov, Fedor
AU - Mueller-Gritschneder, Daniel
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - In modern edge computing, deploying multi-deep neural network (DNN) applications is essential for addressing complex tasks such as visual classification, object tracking, and navigation. The intricate nature of these Machine Learning (ML) applications, coupled with their soft and hard real-time performance requirements, underscores the necessity for automated optimisation of both scheduling and mapping configurations on computationally robust heterogeneous embedded systems. This paper introduces a novel approach for the automated mapping and scheduling of multiple DNNs onto heterogeneous hardware platforms. Our methodology leverages an integer linear program (ILP) scheduler formulation that accommodates soft and hard real-time constraints. This is complemented by a mapping generation process that employs (a) an advanced ILP formulation and (b) a Genetic Algorithm (GA) designed to identify optimised solutions for large-scale mappings. The GA is mainly utilised when the expansive design space renders the ILP formulation impractical in terms of computational solving time. We rigorously test and evaluate our framework using scaling input model configurations and a real-world mixed-model scenario. The results demonstrate that our hybrid optimisation solution, which integrates Prepositional Satisfiability Problem (SAT) decoding, the NSGA-II GA, and ILP, significantly enhances scalability. This improvement is vital for efficiently deploying complex systems, marking a substantial advancement in the embedded ML field.
AB - In modern edge computing, deploying multi-deep neural network (DNN) applications is essential for addressing complex tasks such as visual classification, object tracking, and navigation. The intricate nature of these Machine Learning (ML) applications, coupled with their soft and hard real-time performance requirements, underscores the necessity for automated optimisation of both scheduling and mapping configurations on computationally robust heterogeneous embedded systems. This paper introduces a novel approach for the automated mapping and scheduling of multiple DNNs onto heterogeneous hardware platforms. Our methodology leverages an integer linear program (ILP) scheduler formulation that accommodates soft and hard real-time constraints. This is complemented by a mapping generation process that employs (a) an advanced ILP formulation and (b) a Genetic Algorithm (GA) designed to identify optimised solutions for large-scale mappings. The GA is mainly utilised when the expansive design space renders the ILP formulation impractical in terms of computational solving time. We rigorously test and evaluate our framework using scaling input model configurations and a real-world mixed-model scenario. The results demonstrate that our hybrid optimisation solution, which integrates Prepositional Satisfiability Problem (SAT) decoding, the NSGA-II GA, and ILP, significantly enhances scalability. This improvement is vital for efficiently deploying complex systems, marking a substantial advancement in the embedded ML field.
KW - DSE
KW - ILP
KW - Mapping
KW - multi-DNN
KW - Scheduling
KW - TinyML
UR - http://www.scopus.com/inward/record.url?scp=85202542957&partnerID=8YFLogxK
U2 - 10.1109/COINS61597.2024.10622135
DO - 10.1109/COINS61597.2024.10622135
M3 - Conference contribution
AN - SCOPUS:85202542957
T3 - 2024 IEEE International Conference on Omni-Layer Intelligent Systems, COINS 2024
BT - 2024 IEEE International Conference on Omni-Layer Intelligent Systems, COINS 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 29 July 2024 through 31 July 2024
ER -