TY - GEN
T1 - MPIOV
T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
AU - Munch, Daniel
AU - Paulitsch, Michael
AU - Hanka, Oliver
AU - Herkersdorf, Andreas
N1 - Publisher Copyright:
© 2015 EDAA.
PY - 2015/4/22
Y1 - 2015/4/22
N2 - Safety-critical systems consolidating multiple functionalities of different criticality (so-called mixed-criticality systems) require separation between these functionalities to assure safety and security properties. Performance-hungry and safety-critical applications (like a radar processing system steering an autonomous flying aircraft) may demand an embedded highperformance computing cluster of more than one (multi-core) processor. This paper presents the Multi-Processor I/O Virtualization (MPIOV) concept to enable hardware-based Input/Output (I/O) virtualization or sharing with separation among multiple (multi-core) processors in (mixed-criticality) embedded real-time systems, which usually do not have means for separation like an Input/Output Memory Management Unit (IOMMU). The concept uses a Non-Transparent Bridge (NTB) to connect each processing host to the management host, while checking the target address and source / origin ID to decide whether or not to block a transaction. It is a standardized, portable and non-proprietary platform-independent spatial separation solution that does not require an IOMMU in the processor. Furthermore, the concept sketches an approach for PCI Express (PCIe)-based systems to enable sharing of up to 2048 (virtual) functions per endpoint, while still being compatible to the plain PCIe standard. A practical evaluation demonstrates that the impact to performance degradation (transfer time, transfer rate) is negligible (about 0.01%) compared to a system without separation.
AB - Safety-critical systems consolidating multiple functionalities of different criticality (so-called mixed-criticality systems) require separation between these functionalities to assure safety and security properties. Performance-hungry and safety-critical applications (like a radar processing system steering an autonomous flying aircraft) may demand an embedded highperformance computing cluster of more than one (multi-core) processor. This paper presents the Multi-Processor I/O Virtualization (MPIOV) concept to enable hardware-based Input/Output (I/O) virtualization or sharing with separation among multiple (multi-core) processors in (mixed-criticality) embedded real-time systems, which usually do not have means for separation like an Input/Output Memory Management Unit (IOMMU). The concept uses a Non-Transparent Bridge (NTB) to connect each processing host to the management host, while checking the target address and source / origin ID to decide whether or not to block a transaction. It is a standardized, portable and non-proprietary platform-independent spatial separation solution that does not require an IOMMU in the processor. Furthermore, the concept sketches an approach for PCI Express (PCIe)-based systems to enable sharing of up to 2048 (virtual) functions per endpoint, while still being compatible to the plain PCIe standard. A practical evaluation demonstrates that the impact to performance degradation (transfer time, transfer rate) is negligible (about 0.01%) compared to a system without separation.
KW - IOMMU
KW - IOMPU
KW - hardware-based I/O virtualization
KW - mixed-criticality systems
KW - multi-core
KW - multiprocessor
KW - non-transparent bridge (NTB)
KW - real-time embedded systems
KW - spatial separation
UR - http://www.scopus.com/inward/record.url?scp=84945920357&partnerID=8YFLogxK
U2 - 10.7873/date.2015.0218
DO - 10.7873/date.2015.0218
M3 - Conference contribution
AN - SCOPUS:84945920357
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 579
EP - 584
BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 March 2015 through 13 March 2015
ER -