TY - JOUR
T1 - Monitoring cache behavior on parallel SMP architectures and related programming tools
AU - Brandes, Thomas
AU - Schwamborn, Helmut
AU - Gerndt, Michael
AU - Jeitner, Jürgen
AU - Kereku, Edmond
AU - Schulz, Martin
AU - Brunst, Holger
AU - Nagel, Wolfgang
AU - Neumann, Reinhard
AU - Müller-Pfefferkorn, Ralph
AU - Trenkler, Bernd
AU - Karl, Wolfgang
AU - Tao, Jie
AU - Hoppe, Hans Christian
N1 - Funding Information:
The project EP-CACHE [5] (funded by the German Federal Ministry of Education and Research, BMBF) is intended to overcome this problem. By exploiting hardware monitors and related monitor control techniques the user can gain more useful information about the cache behavior in his program. Related tools for monitor controlling, performance visualization and optimization provide new and advanced possibilities for the identification of memory-cache problems and their elimination. The tools address the analysis and the optimization of programs for cache architectures, especially for SMP clusters.
PY - 2005/10
Y1 - 2005/10
N2 - This paper describes the ideas and developments of the project EP-CACHE. Within this project new methods and tools are developed to improve the analysis and the optimization of programs for cache architectures, especially for SMP clusters. The tool set comprises the semi-automatic instrumentation of user programs, the monitoring of the cache behavior, the visualization of the measured data, and optimization techniques for improving the user program for better cache usage. As current hardware performance counters do not give sufficient user relevant information, new hardware monitors are designed that provide more detailed information about the cache utilization related to the data structures and code blocks in the user program. The expense of the hardware and software realization will be assessed to minimize the risk of a real implementation of the investigated monitors. The usefulness of the hardware monitors is evaluated by a cache simulator.
AB - This paper describes the ideas and developments of the project EP-CACHE. Within this project new methods and tools are developed to improve the analysis and the optimization of programs for cache architectures, especially for SMP clusters. The tool set comprises the semi-automatic instrumentation of user programs, the monitoring of the cache behavior, the visualization of the measured data, and optimization techniques for improving the user program for better cache usage. As current hardware performance counters do not give sufficient user relevant information, new hardware monitors are designed that provide more detailed information about the cache utilization related to the data structures and code blocks in the user program. The expense of the hardware and software realization will be assessed to minimize the risk of a real implementation of the investigated monitors. The usefulness of the hardware monitors is evaluated by a cache simulator.
KW - Cache optimizations
KW - Hardware cache monitoring
KW - Parallel programming tools
KW - Performance analysis
KW - SMP cluster
UR - http://www.scopus.com/inward/record.url?scp=24044464525&partnerID=8YFLogxK
U2 - 10.1016/j.future.2004.09.005
DO - 10.1016/j.future.2004.09.005
M3 - Article
AN - SCOPUS:24044464525
SN - 0167-739X
VL - 21
SP - 1298
EP - 1311
JO - Future Generation Computer Systems
JF - Future Generation Computer Systems
IS - 8
ER -