TY - GEN
T1 - Modular system-level architecture for concurrent cell balancing
AU - Kauer, Matthias
AU - Naranayaswami, Swaminathan
AU - Steinhorst, Sebastian
AU - Lukasiewycz, Martin
AU - Chakraborty, Samarjit
AU - Hedrich, Lars
PY - 2013
Y1 - 2013
N2 - This paper proposes a novel modular architecture for Electrical Energy Storages (EESs), consisting of multiple seriesconnected cells. In contrast to state-of-the-art architectures, the presented approach significantly improves the energy utilization, safety, and availability of EESs. For this purpose, each cell is equipped with a circuit that enables an individual control within a homogeneous architecture. One major advantage of our approach is a direct and concurrent charge transfer between each cell of the EES using inductors. To enable a system-level modeling and performance analysis of the architecture, a detailed investigation of the components and their interaction with the Pulse Width Modulation (PWM) control was performed at transistor-level. At system-level, we propose a control algorithm for the charge transfer that aims at minimizing the energy loss and balancing time. The results give evidence of the significant advantages of our architecture over existing passive and active balancing methods in terms of energy eficiency and charge equalization time. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles General Terms: Algorithms, Design.
AB - This paper proposes a novel modular architecture for Electrical Energy Storages (EESs), consisting of multiple seriesconnected cells. In contrast to state-of-the-art architectures, the presented approach significantly improves the energy utilization, safety, and availability of EESs. For this purpose, each cell is equipped with a circuit that enables an individual control within a homogeneous architecture. One major advantage of our approach is a direct and concurrent charge transfer between each cell of the EES using inductors. To enable a system-level modeling and performance analysis of the architecture, a detailed investigation of the components and their interaction with the Pulse Width Modulation (PWM) control was performed at transistor-level. At system-level, we propose a control algorithm for the charge transfer that aims at minimizing the energy loss and balancing time. The results give evidence of the significant advantages of our architecture over existing passive and active balancing methods in terms of energy eficiency and charge equalization time. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles General Terms: Algorithms, Design.
KW - Active cell balancing
KW - Battery management
KW - Charge equalization
KW - Modeling
KW - Simulation
UR - http://www.scopus.com/inward/record.url?scp=84879853722&partnerID=8YFLogxK
U2 - 10.1145/2463209.2488926
DO - 10.1145/2463209.2488926
M3 - Conference contribution
AN - SCOPUS:84879853722
SN - 9781450320719
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 50th Annual Design Automation Conference, DAC 2013
T2 - 50th Annual Design Automation Conference, DAC 2013
Y2 - 29 May 2013 through 7 June 2013
ER -