Model-based framework for networks-on-chip design space exploration

Keyphrases

• Design Space Exploration 100%
• NoC Design 100%
• Network-on-chip Design 100%
• NoCs 100%
• Model-based Framework 100%
• Latency 50%
• Network on chip 50%
• Evaluation Model 50%
• Eclipse Modeling Framework 50%
• Router Architecture 50%
• Orion 50%
• Multimedia Applications 50%
• Application Traffic 50%
• Routing Algorithm 50%
• NoC Topology 50%
• Verilog 50%
• NoC Routing 50%
• Topology Algorithm 50%
• Increased Density 50%
• Code Generation 50%
• Random Traffic 50%
• Large Design Space 50%

Computer Science

• Design-Space Exploration 100%
• Networks on Chips 100%
• SystemC 50%
• Evaluation Models 50%
• Buffer Utilization 50%
• Modeling Framework 50%
• Code Generation 50%
• Multimedia Application 50%
• Verilog 50%
• Router Architecture 50%
• Routing Algorithm 50%