Minimizing spurious switching activities in CMOS circuits

Keyphrases

• CMOS Circuits 100%
• Switching Activity 100%
• Path Delay 100%
• Logic Gates 100%
• Transistor Size 100%
• Transistor 100%
• Power Consumption 50%
• Negative Influence 50%
• Delay Difference 50%
• Delay Path 50%
• Circuit Power Consumption 50%
• Design Objectives 50%
• Power Dissipated 50%
• Balance Delay 50%
• Channel Width 50%
• Short-circuit Power 50%
• Gate Capacitance 50%
• Static CMOS 50%
• Transistor Sizing 50%
• Propagation Delay 50%
• Zero Delay 50%
• Multi-objective Optimization Problem 50%
• Total Capacitance 50%
• Signal Slope 50%

Computer Science

• Power Consumption 100%
• Logic Gate 100%
• Switching Activity 100%
• Optimization Problem 50%
• Multiobjective 50%
• Total Capacitance 50%
• Propagation Delay 50%
• Design Objective 50%
• Gate Capacitance 50%

Engineering

• Electric Power Utilization 100%
• Logic Gate 100%
• Switching Activity 100%
• Design Objective 50%
• Delay Difference 50%
• Multiobjective Optimization Problem 50%
• Gate Capacitance 50%
• Propagation Delay 50%