TY - GEN
T1 - MaskVer
T2 - 1st IEEE International Verification and Security Workshop, IVSW 2016
AU - Tempelmeier, Michael
AU - Sigl, Georg
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/9/13
Y1 - 2016/9/13
N2 - Hardening cryptographic algorithms against sidechannel attacks is a complex but crucial task in today's hardware implementations. One of the most promising countermeasures is Boolean Masking. Designers spend much effort to optimise and customise their masking schemes, but many proposed masked implementations were eventually broken, because they are somehow flawed-not necessarily restricted to a specific error, but to an overall leakage problem. As today's EDA tools hardly support masking, the masking process is still a manual task for the designer. Even worse, due to the lack of capable EDA tools, after synthesis there is no guarantee that the masking still applies and is not optimised. Checking each and every gate of a netlist for masking flaws after synthesis is a time consuming, expensive, and infeasible task. In this paper, we propose a graph based method to reduce the number of gates to be checked. We also present a prototype implementation of our tool to help designers detecting flawed masking in their designs.
AB - Hardening cryptographic algorithms against sidechannel attacks is a complex but crucial task in today's hardware implementations. One of the most promising countermeasures is Boolean Masking. Designers spend much effort to optimise and customise their masking schemes, but many proposed masked implementations were eventually broken, because they are somehow flawed-not necessarily restricted to a specific error, but to an overall leakage problem. As today's EDA tools hardly support masking, the masking process is still a manual task for the designer. Even worse, due to the lack of capable EDA tools, after synthesis there is no guarantee that the masking still applies and is not optimised. Checking each and every gate of a netlist for masking flaws after synthesis is a time consuming, expensive, and infeasible task. In this paper, we propose a graph based method to reduce the number of gates to be checked. We also present a prototype implementation of our tool to help designers detecting flawed masking in their designs.
KW - Boolean masking
KW - EDA
KW - differential power analysis (DPA)
KW - directed acyclic graph (DAG)
KW - hardware verification
KW - side-channel analysis
UR - https://www.scopus.com/pages/publications/84992166435
U2 - 10.1109/IVSW.2016.7566602
DO - 10.1109/IVSW.2016.7566602
M3 - Conference contribution
AN - SCOPUS:84992166435
T3 - 2016 1st IEEE International Verification and Security Workshop, IVSW 2016
SP - 25
EP - 30
BT - 2016 1st IEEE International Verification and Security Workshop, IVSW 2016
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 4 July 2016 through 6 July 2016
ER -