MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs

Many embedded systems such as automotive and industrial Micro-Controller Units (MCUs) use on-chip SRAM as main data memory of the embedded processor. However, SRAMs are increasingly susceptible to reliability threats such as Bias Temperature Instability (BTI) due to the continuous trend of technology shrinking. BTI leads to a significant performance degradation, especially in the Sense Amplifiers (SAs) of SRAMs, where failures are fatal, since the data of a whole column is destroyed. As countermeasure, usually guardbands are added to the design to prevent failures of the embedded system before its end of life. In this paper we present the Mitigation of AGIng Circuitry (MAGIC), a low-cost circuitry to effectively mitigate aging in SAs by wear-leveling. The circuitry consists of an array of XOR gates and a counter. MAGIC modifies the mapping of SRAM banks to physical addresses. Updating the counter value distributes the stress of highly used addresses, e.g., corresponding to program stack data, onto the complete SRAM array. We evaluate the wear-out for on-chip SRAM data memory loads of a typical embedded application. MAGIC mitigates SA degradation up to 50% for three years of aging while introducing minimal area/performance overhead.