Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor (Invited Paper)

In ever-shrinking technology nodes, where transistor 3D structures become increasingly confined and their features verge on the atomic scale, the phenomena of aging and self-heating have ascended as critical reliability concerns. This paper addresses the intricate challenge of estimating the impact of aging and self-heating, a task that requires bridging the gap between semiconductor device physics - the genesis of these mechanisms - and the processor level, where the induced degradations ultimately culminate in tangible errors. The complexity of this task is further amplified by the pivotal role of temperature in reliability estimations. Temperature is not merely a factor but a key driver in the dynamics of aging processes, influencing both the acceleration and the mitigation (i.e., recovery and annealing) of aging-induced degradation. Based on silicon measurements from 28 nm planar MOSFETs and 16 nm FinFET circuits, we contrast recovery with annealing and demonstrate the essential role of temperature and time in aging mitigation. Recovery and annealing must be considered to obtain accurate reliability estimations and exploited to minimize the impact of aging. In response to these challenges, our work introduces advanced machine learning (ML) techniques as innovative solutions for the EDA industry to accurately estimate the impact of aging and self-heating from individual transistors to complex circuits like full processors under the effects of workload activities. Our ML techniques allow designers to estimate the effects of these phenomena without sharing physics-based models, which are often proprietary and confidential. We present the effective integration of sign-off tools for estimating self-heating across a whole processor at the GDS level, showcasing a significant advancement in processor reliability analysis.