TY - GEN
T1 - Low-voltage PowerMOSFETs used as dissipative elements
T2 - 37th IEEE Power Electronics Specialists Conference 2006, PESC'06
AU - Castellazzi, Alberto
AU - Wachutka, Gerhard
PY - 2006
Y1 - 2006
N2 - This paper deals with the use of low-voltage PowerMOSFETs as protective elements within a circuit. Examples taken from a modern application scenario are discussed, showing that the transistors must be capable of withstanding high power dissipation under very diverse bias conditions, spanning the whole range of their transfer-characteristics. A comprehensive experimental characterization is presented. Two working conditions are considered in particular, short-circuit and thermally unstable operation: they are both associated with considerable heat-generation and temperature increase within the silicon chip, implying a risk for the safe operation of the transistors. The differences between one case and the other and the problems associated with each of them are underlined. For greater insight, then, electrothermal 2D device-simulation is employed. A comparative analysis is carried out, highlighting those features which can be considered typical of the relevant operational mode. Finally, the influence of parasitic bipolar currents onto the eventual failure of the PowerMOSFETs is discussed. They are due to thermal generation of electron-hole pairs and to the high value of the drain-source voltage involved and can lead to activation of the parasitic BJT and to the catastrophic failure of the transistor.
AB - This paper deals with the use of low-voltage PowerMOSFETs as protective elements within a circuit. Examples taken from a modern application scenario are discussed, showing that the transistors must be capable of withstanding high power dissipation under very diverse bias conditions, spanning the whole range of their transfer-characteristics. A comprehensive experimental characterization is presented. Two working conditions are considered in particular, short-circuit and thermally unstable operation: they are both associated with considerable heat-generation and temperature increase within the silicon chip, implying a risk for the safe operation of the transistors. The differences between one case and the other and the problems associated with each of them are underlined. For greater insight, then, electrothermal 2D device-simulation is employed. A comparative analysis is carried out, highlighting those features which can be considered typical of the relevant operational mode. Finally, the influence of parasitic bipolar currents onto the eventual failure of the PowerMOSFETs is discussed. They are due to thermal generation of electron-hole pairs and to the high value of the drain-source voltage involved and can lead to activation of the parasitic BJT and to the catastrophic failure of the transistor.
UR - http://www.scopus.com/inward/record.url?scp=42449112107&partnerID=8YFLogxK
U2 - 10.1109/PESC.2006.1711878
DO - 10.1109/PESC.2006.1711878
M3 - Conference contribution
AN - SCOPUS:42449112107
SN - 0780397169
SN - 9780780397163
T3 - PESC Record - IEEE Annual Power Electronics Specialists Conference
BT - 37th IEEE Power Electronics Specialists Conference 2006, PESC'06
Y2 - 18 June 2006 through 22 June 2006
ER -