Abstract
Datapath architectures exhibit a large amount of undesired switching (glitches) which does not contribute to the functionality but leads to increased power consumption. While glitch propagation can be effectively reduced by pipelining circuits with acyclic SFGs, this technique is not directly applicable if the circuit contains loops. The paper addresses this problem and discusses a methodology for reducing switching activity in recursive circuits. Simulation results of a few example circuits follow.
Original language | English |
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Pages (from-to) | II-597-II-600 |
Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
Volume | 2 |
DOIs | |
State | Published - 2000 |
Event | Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 28 May 2000 → 31 May 2000 |