Low power transformation of datapath architectures with cyclic SFGs

Marek Wroblewski, Sven Simon, Josef A. Nossek

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

Datapath architectures exhibit a large amount of undesired switching (glitches) which does not contribute to the functionality but leads to increased power consumption. While glitch propagation can be effectively reduced by pipelining circuits with acyclic SFGs, this technique is not directly applicable if the circuit contains loops. The paper addresses this problem and discusses a methodology for reducing switching activity in recursive circuits. Simulation results of a few example circuits follow.

Original languageEnglish
Pages (from-to)II-597-II-600
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 2000
EventProceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland
Duration: 28 May 200031 May 2000

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