Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier

Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

In the past few years, there has been a growing interest in Curve25519 due to its elegant design aimed at both high-security and high-performance, making it one of the most promising candidates to secure IoT applications. Until now Curve25519 hardware implementations were mainly optimized for high-throughput applications, while no special care was given to low-latency designs. In this work, we close this gap and provide a Curve25519 hardware design targeting low-latency applications. We present a fast constant-time variable-base-point elliptic curve scalar multiplication using Curve25519 that computes a session key in less than 100 μs. This is achieved by using a high-speed prime field multiplier that smartly combines the reduction procedure with the summation of the digit-products. As a result, our presented implementation requires only 10465 cycles for one session key computation. Synthesized on a Zynq-7030 and operating with a clock frequency of 115 MHz this translates to a latency of 92 μs which represents an improvement of factor 3.2 compared to other Curve25519 implementations. Our implementation uses Montgomery ladder as the scalar multiplication algorithm and includes randomized projective coordinates to thwart side-channel attacks.

Original languageEnglish
Pages (from-to)491-497
Number of pages7
JournalMicroprocessors and Microsystems
Volume52
DOIs
StatePublished - Jul 2017

Keywords

  • Curve25519
  • ECC
  • ECDH
  • FPGA
  • X25519
  • Zynq

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