TY - GEN
T1 - Logic locking induced fault attacks
AU - Brunner, Michaela
AU - Gruber, Michael
AU - Tempelmeier, Michael
AU - Sigl, Georg
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/7
Y1 - 2020/7
N2 - Logic locking has been presented in the past as a solution to avoid overproduction or product piracy. All solutions so far assume or rely on the protection of the correct locking key. This paper does not target the break of locking schemes but looks at another highly critical security risk which comes with modified locking keys: The enabling of fault attacks. We will analyze the applicability of the risk based on different logic locking methods, key management techniques, and fault analysis techniques. Additionally, we will demonstrate its threat by a modified template based persistent fault analysis on an AES implementation. There, the fault injection is realized by randomly inserted locking gates and a permanently modified locking key.
AB - Logic locking has been presented in the past as a solution to avoid overproduction or product piracy. All solutions so far assume or rely on the protection of the correct locking key. This paper does not target the break of locking schemes but looks at another highly critical security risk which comes with modified locking keys: The enabling of fault attacks. We will analyze the applicability of the risk based on different logic locking methods, key management techniques, and fault analysis techniques. Additionally, we will demonstrate its threat by a modified template based persistent fault analysis on an AES implementation. There, the fault injection is realized by randomly inserted locking gates and a permanently modified locking key.
KW - Fault attack
KW - Hardware Trojan
KW - Logic locking
KW - Persistent fault analysis
KW - S-box
UR - http://www.scopus.com/inward/record.url?scp=85090405289&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI49217.2020.00030
DO - 10.1109/ISVLSI49217.2020.00030
M3 - Conference contribution
AN - SCOPUS:85090405289
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 114
EP - 119
BT - Proceedings - 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
PB - IEEE Computer Society
T2 - 19th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020
Y2 - 6 July 2020 through 8 July 2020
ER -