Leveraging CPU-FPGA Co-design for Matrix Profile Computation

Current technology trends in high-performance computing (HPC) are pushing us towards accelerated systems. While GPU-based systems are the most common option, not all applications work well on such architectures. Solutions, like programmable hardware in the form of FPGAs (Field Programmable Gate Arrays), can be a powerful alternative. However, the complexity of developing specialized computing units in FPGAs, which are optimized for a specific task, often limits their broad utilization. In this paper, we follow a co-design methodology to identify the key computational routines and to replace them by using user-friendly libraries that wrap complex FPGA access mechanisms. This simplifies the usage of specialized compute units in FPGAs. To demonstrate our approach, we focus on performance improvements for an HPC/BigData application called (MP)^N, which is built around widely used data analytics algorithm computing the matrix profile for multidimensional time series. In this application, we identify a sorting kernel as one of the key time consumers and accelerate it designing a parallel sorting library and using it to offload sorting batches to the FPGA. At the same time, we enable efficient utilization of CPU resources through overlap and pipelining. We achieve a 2-fold run time improvement for computing a 128-dimensional time series of 7 million records, with the performance gap increasing as the number of records grows, highlighting the potential of CPU-FPGA co-design in HPC.