@inproceedings{83d9fe41f7ef4a56bb579538fe76cfdc,
title = "Layout options for stability tuning of SRAM cells in Multi-Gate-FET technologies",
abstract = "We present an investigation of different layout options for Multi-Gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static Noise Margins (SNM) of 210mV have been measured at 1V VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.",
author = "F. Bauer and {Von Arnim}, K. and C. Pacha and T. Schulz and M. Fulde and A. Nackaerts and M. Jurczak and W. Xiong and San, {K. T.} and Cleavelin, {C. R.} and K. Schr{\"u}fer and G. Georgakos and D. Schmitt-Landsiedel",
year = "2007",
doi = "10.1109/ESSCIRC.2007.4430325",
language = "English",
isbn = "1424411254",
series = "ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference",
pages = "392--395",
booktitle = "ESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference",
note = "ESSCIRC 2007 - 33rd European Solid-State Circuits Conference ; Conference date: 11-09-2007 Through 13-09-2007",
}