Layout options for stability tuning of SRAM cells in Multi-Gate-FET technologies

F. Bauer, K. Von Arnim, C. Pacha, T. Schulz, M. Fulde, A. Nackaerts, M. Jurczak, W. Xiong, K. T. San, C. R. Cleavelin, K. Schrüfer, G. Georgakos, D. Schmitt-Landsiedel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

We present an investigation of different layout options for Multi-Gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static Noise Margins (SNM) of 210mV have been measured at 1V VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.

Original languageEnglish
Title of host publicationESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
Pages392-395
Number of pages4
DOIs
StatePublished - 2007
EventESSCIRC 2007 - 33rd European Solid-State Circuits Conference - Munich, Germany
Duration: 11 Sep 200713 Sep 2007

Publication series

NameESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2007 - 33rd European Solid-State Circuits Conference
Country/TerritoryGermany
CityMunich
Period11/09/0713/09/07

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