LAUFZEITABSCHAETZUNG AN CMOS-GATTERN: LOGIKSCHALTUNGEN AUCH OHNE SIMULATION DIMENSIONIEREN.

Thomas Kling; Walter Stechele; Ingolf Ruge

LAUFZEITABSCHAETZUNG AN CMOS-GATTERN: LOGIKSCHALTUNGEN AUCH OHNE SIMULATION DIMENSIONIEREN.

Translated title of the contribution: Estimation of Delay Time of CMOS Gates: Design of Logic Circuits also without Simulation.

Thomas Kling
, Walter Stechele
, Ingolf Ruge

Chair of Integrated Systems

Research output: Contribution to journal › Article › peer-review

Abstract

A simple analytic delay time model for CMOS circuits is presented. It represents a relationship between expected logic combination, design of the transistors and the delay time in the circuit. The model can be used to derive rules for the design of a logic circuit and the distribution of gates with multiple inputs in cascade networks.

Translated title of the contribution	Estimation of Delay Time of CMOS Gates: Design of Logic Circuits also without Simulation.
Original language	German
Pages (from-to)	91-96
Number of pages	6
Journal	Elektronik
Volume	37
Issue number	4
State	Published - 1 Jan 1988

Cite this

@article{31c4bee0148649c19eaa5c8afa7e9d87,

title = "LAUFZEITABSCHAETZUNG AN CMOS-GATTERN: LOGIKSCHALTUNGEN AUCH OHNE SIMULATION DIMENSIONIEREN.",

abstract = "A simple analytic delay time model for CMOS circuits is presented. It represents a relationship between expected logic combination, design of the transistors and the delay time in the circuit. The model can be used to derive rules for the design of a logic circuit and the distribution of gates with multiple inputs in cascade networks.",

author = "Thomas Kling and Walter Stechele and Ingolf Ruge",

year = "1988",

month = jan,

day = "1",

language = "Deutsch",

volume = "37",

pages = "91--96",

journal = "Elektronik",

issn = "0013-5658",

number = "4",

}

TY - JOUR

T1 - LAUFZEITABSCHAETZUNG AN CMOS-GATTERN

T2 - LOGIKSCHALTUNGEN AUCH OHNE SIMULATION DIMENSIONIEREN.

AU - Kling, Thomas

AU - Stechele, Walter

AU - Ruge, Ingolf

PY - 1988/1/1

Y1 - 1988/1/1

N2 - A simple analytic delay time model for CMOS circuits is presented. It represents a relationship between expected logic combination, design of the transistors and the delay time in the circuit. The model can be used to derive rules for the design of a logic circuit and the distribution of gates with multiple inputs in cascade networks.

AB - A simple analytic delay time model for CMOS circuits is presented. It represents a relationship between expected logic combination, design of the transistors and the delay time in the circuit. The model can be used to derive rules for the design of a logic circuit and the distribution of gates with multiple inputs in cascade networks.

UR - https://www.scopus.com/pages/publications/0023963931

M3 - Artikel

AN - SCOPUS:0023963931

SN - 0013-5658

VL - 37

SP - 91

EP - 96

JO - Elektronik

JF - Elektronik

IS - 4

ER -

LAUFZEITABSCHAETZUNG AN CMOS-GATTERN: LOGIKSCHALTUNGEN AUCH OHNE SIMULATION DIMENSIONIEREN.

Abstract

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