Abstract
A simple analytic delay time model for CMOS circuits is presented. It represents a relationship between expected logic combination, design of the transistors and the delay time in the circuit. The model can be used to derive rules for the design of a logic circuit and the distribution of gates with multiple inputs in cascade networks.
| Translated title of the contribution | Estimation of Delay Time of CMOS Gates: Design of Logic Circuits also without Simulation. |
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| Original language | German |
| Pages (from-to) | 91-96 |
| Number of pages | 6 |
| Journal | Elektronik |
| Volume | 37 |
| Issue number | 4 |
| State | Published - 1 Jan 1988 |