Latched CMOS DRAM sense amplifier yield analysis and optimization

Yan Li; Helmut Schneider; Florian Schnabel; Roland Thewes; Doris Schmitt-Landsiedel

doi:10.1007/978-3-540-95948-9_13

Latched CMOS DRAM sense amplifier yield analysis and optimization

Yan Li
, Helmut Schneider
, Florian Schnabel
, Roland Thewes
, Doris Schmitt-Landsiedel

Medicine and Health

Technical University of Munich
Qimonda AG i IN

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.

Original language	English
Pages (from-to)	126-135
Number of pages	10
Journal	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	5349 LNCS
DOIs	https://doi.org/10.1007/978-3-540-95948-9_13
State	Published - 2009
Event	18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - Lisbon, Portugal Duration: 10 Sep 2008 → 12 Sep 2008

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10.1007/978-3-540-95948-9_13

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title = "Latched CMOS DRAM sense amplifier yield analysis and optimization",

abstract = "Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.",

author = "Yan Li and Helmut Schneider and Florian Schnabel and Roland Thewes and Doris Schmitt-Landsiedel",

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note = "18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 ; Conference date: 10-09-2008 Through 12-09-2008",

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Latched CMOS DRAM sense amplifier yield analysis and optimization. / Li, Yan; Schneider, Helmut; Schnabel, Florian et al.
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 5349 LNCS, 2009, p. 126-135.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - Latched CMOS DRAM sense amplifier yield analysis and optimization

AU - Li, Yan

AU - Schneider, Helmut

AU - Schnabel, Florian

AU - Thewes, Roland

AU - Schmitt-Landsiedel, Doris

PY - 2009

Y1 - 2009

N2 - Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.

AB - Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.

UR - https://www.scopus.com/pages/publications/61649121600

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DO - 10.1007/978-3-540-95948-9_13

M3 - Conference article

AN - SCOPUS:61649121600

SN - 0302-9743

VL - 5349 LNCS

SP - 126

EP - 135

JO - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

JF - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

T2 - 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008

Y2 - 10 September 2008 through 12 September 2008

ER -

Latched CMOS DRAM sense amplifier yield analysis and optimization

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