Latched CMOS DRAM sense amplifier yield analysis and optimization

Yan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.

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