TY - JOUR
T1 - Latched CMOS DRAM sense amplifier yield analysis and optimization
AU - Li, Yan
AU - Schneider, Helmut
AU - Schnabel, Florian
AU - Thewes, Roland
AU - Schmitt-Landsiedel, Doris
PY - 2009
Y1 - 2009
N2 - Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.
AB - Aiming for a systematic evaluation of DRAM sense amplifier (SA) performance, the SA is modeled using small signal equivalent circuit approach in order to analyze mismatch effects and to support design robustness concerning technology variations. The statistical mismatch of the SA is replaced by equivalent voltage sources. The switching delay between n- and p-sensing transistors of the SA is also analyzed. This approach supports yield consideration of DRAM sense amplifiers in future technologies.
UR - http://www.scopus.com/inward/record.url?scp=61649121600&partnerID=8YFLogxK
U2 - 10.1007/978-3-540-95948-9_13
DO - 10.1007/978-3-540-95948-9_13
M3 - Conference article
AN - SCOPUS:61649121600
SN - 0302-9743
VL - 5349 LNCS
SP - 126
EP - 135
JO - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
JF - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
T2 - 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008
Y2 - 10 September 2008 through 12 September 2008
ER -