Large Language Model-Based Optimization for System-Level Test Program Generation

  • Denis Schwachhofer
  • , Peter Domanski
  • , Steffen Becker
  • , Stefan Wagner
  • , Matthias Sauer
  • , Dirk Pfluger
  • , Ilia Polian

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description.

Original languageEnglish
Title of host publication37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350366884
DOIs
StatePublished - 2024
Event37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024 - Didcot, United Kingdom
Duration: 8 Oct 202410 Oct 2024

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN (Print)2576-1501
ISSN (Electronic)2765-933X

Conference

Conference37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
Country/TerritoryUnited Kingdom
CityDidcot
Period8/10/2410/10/24

Keywords

  • Functional Test
  • Large Language Models
  • Optimization
  • System-Level Test
  • Test Generation

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