TY - GEN
T1 - Integrated synthesis of linear nearest neighbor Ancilla-free MCT circuits
AU - Rahman, Md Mazder
AU - Dueck, Gerhard W.
AU - Chattopadhyay, Anupam
AU - Wille, Robert
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/18
Y1 - 2016/7/18
N2 - The rapid advances of quantum technologiesare opening up new challenges, of which, protectingquantum states from errors is a major one. Amongquantum error correction schemes, the surface code isemerging as a natural choice with high-fidelity quantumgates reported for experimental platforms. Surfacecodes also necessitate the quantum gates to be formedwith strict nearest neighbour coupling. State-of-the-artreversible logic synthesis techniques for quantum circuitimplementation do not ensure the logic gates to be formedin a nearest neighbor fashion, and this is handled as a post processingoptimization by the insertion of swap gates. Inthis paper, we propose, for the first time, the inclusionof nearest neighbourhood criteria in a widely used ancilla freereversible logic synthesis method. Experimental resultsshow that this method easily outperforms the earlier two steptechniques in terms of gate count without any runtime overhead.
AB - The rapid advances of quantum technologiesare opening up new challenges, of which, protectingquantum states from errors is a major one. Amongquantum error correction schemes, the surface code isemerging as a natural choice with high-fidelity quantumgates reported for experimental platforms. Surfacecodes also necessitate the quantum gates to be formedwith strict nearest neighbour coupling. State-of-the-artreversible logic synthesis techniques for quantum circuitimplementation do not ensure the logic gates to be formedin a nearest neighbor fashion, and this is handled as a post processingoptimization by the insertion of swap gates. Inthis paper, we propose, for the first time, the inclusionof nearest neighbourhood criteria in a widely used ancilla freereversible logic synthesis method. Experimental resultsshow that this method easily outperforms the earlier two steptechniques in terms of gate count without any runtime overhead.
UR - http://www.scopus.com/inward/record.url?scp=84981294905&partnerID=8YFLogxK
U2 - 10.1109/ISMVL.2016.54
DO - 10.1109/ISMVL.2016.54
M3 - Conference contribution
AN - SCOPUS:84981294905
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 144
EP - 149
BT - Proceedings - 2016 IEEE 46th International Symposium on Multiple-Valued Logic, ISMVL 2016
PB - IEEE Computer Society
T2 - 46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016
Y2 - 18 May 2016 through 20 May 2016
ER -