Integrated Soft Error Resilience and Self-Test

Erol Koser; Sebastian Krosche; Walter Stechele

doi:10.1109/VLSI-SoC.2016.7753569

Integrated Soft Error Resilience and Self-Test

Erol Koser, Sebastian Krosche, Walter Stechele

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Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Many VLSI-SoC include both, protection against soft errors and Built-In-Self-Test (BIST). This work investigates on the combination of both domains. The proposed approach offers additional functionality for BIST, i.e. self-test capabilities for the test logic itself and fault localization. A snapshot mode is offered as well. It enables the taking of snapshots of the current system state concurrently to task execution. The new approach was implemented and verified in various test circuits. The resource overhead is approx. 15 % in registers and 37 % in LUTs when synthesized for a FPGA, as compared to simple superposition of the initial approaches.

Original language	English
Title of host publication	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509035618
DOIs	https://doi.org/10.1109/VLSI-SoC.2016.7753569
State	Published - 22 Nov 2016
Event	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 - Tallinn, Estonia Duration: 26 Sep 2016 → 28 Sep 2016

Publication series

Name	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Conference

Conference	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Country/Territory	Estonia
City	Tallinn
Period	26/09/16 → 28/09/16

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10.1109/VLSI-SoC.2016.7753569

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Koser, E., Krosche, S., & Stechele, W. (2016). Integrated Soft Error Resilience and Self-Test. In 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 Article 7753569 (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-SoC.2016.7753569

@inproceedings{8c18c6eaa2be49dc84471f311456c7d9,

title = "Integrated Soft Error Resilience and Self-Test",

abstract = "Many VLSI-SoC include both, protection against soft errors and Built-In-Self-Test (BIST). This work investigates on the combination of both domains. The proposed approach offers additional functionality for BIST, i.e. self-test capabilities for the test logic itself and fault localization. A snapshot mode is offered as well. It enables the taking of snapshots of the current system state concurrently to task execution. The new approach was implemented and verified in various test circuits. The resource overhead is approx. 15 % in registers and 37 % in LUTs when synthesized for a FPGA, as compared to simple superposition of the initial approaches.",

author = "Erol Koser and Sebastian Krosche and Walter Stechele",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 ; Conference date: 26-09-2016 Through 28-09-2016",

year = "2016",

month = nov,

day = "22",

doi = "10.1109/VLSI-SoC.2016.7753569",

language = "English",

series = "2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016",

}

Koser, E, Krosche, S & Stechele, W 2016, Integrated Soft Error Resilience and Self-Test. in 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016., 7753569, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Institute of Electrical and Electronics Engineers Inc., 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, 26/09/16. https://doi.org/10.1109/VLSI-SoC.2016.7753569

Integrated Soft Error Resilience and Self-Test. / Koser, Erol; Krosche, Sebastian; Stechele, Walter.
2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7753569 (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Integrated Soft Error Resilience and Self-Test

AU - Koser, Erol

AU - Krosche, Sebastian

AU - Stechele, Walter

PY - 2016/11/22

Y1 - 2016/11/22

N2 - Many VLSI-SoC include both, protection against soft errors and Built-In-Self-Test (BIST). This work investigates on the combination of both domains. The proposed approach offers additional functionality for BIST, i.e. self-test capabilities for the test logic itself and fault localization. A snapshot mode is offered as well. It enables the taking of snapshots of the current system state concurrently to task execution. The new approach was implemented and verified in various test circuits. The resource overhead is approx. 15 % in registers and 37 % in LUTs when synthesized for a FPGA, as compared to simple superposition of the initial approaches.

AB - Many VLSI-SoC include both, protection against soft errors and Built-In-Self-Test (BIST). This work investigates on the combination of both domains. The proposed approach offers additional functionality for BIST, i.e. self-test capabilities for the test logic itself and fault localization. A snapshot mode is offered as well. It enables the taking of snapshots of the current system state concurrently to task execution. The new approach was implemented and verified in various test circuits. The resource overhead is approx. 15 % in registers and 37 % in LUTs when synthesized for a FPGA, as compared to simple superposition of the initial approaches.

UR - http://www.scopus.com/inward/record.url?scp=85006725037&partnerID=8YFLogxK

U2 - 10.1109/VLSI-SoC.2016.7753569

DO - 10.1109/VLSI-SoC.2016.7753569

M3 - Conference contribution

AN - SCOPUS:85006725037

T3 - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

BT - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Y2 - 26 September 2016 through 28 September 2016

ER -

Integrated Soft Error Resilience and Self-Test

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