Influence of transistor degradation on CMOS performance and impact on life time criterion

For more realistic lifetime predictions of CMOS technology a stress test was developed that yields the relevant transistor degradation under dynamic stress and simultaneously the impact of transistor degradation on circuit speed performance. Thus uncertainties with respect to duty factor estimations and special dynamic effects are eliminated. The influence on circuit performance can be directly characterized by the change of ring oscillator frequency. The relative frequency change was found to be about one order of magnitude similar than the transconductance change. Based on these results, a less restrictive lifetime criterion is introduced. If 1-2% frequency change is allowed the acceptable Δg_m/g_m (where g_m is the extrinsic transconductance) can be increased from the typical value of 10% to 25%, resulting in an considerably increased lifetime. For a given lifetime this can be utilized to reduce the gate length from 1 μm to 0.4 μm without reducing the supply voltage, extending the use of 5-V supply voltage into the deep sub-μm regime.