In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures

Scalable communication and low latency memory accesses are the deciding factors for future manycore performance. An efficient hardware infrastructure is required, since raw performance must be balanced with area and power constraints. In distributed shared-memory (DSM) architectures, caches help in reducing costly remote accesses but must be kept coherent. To enable scalable coherence in manycore systems, the recently proposed region-based cache coherence defines configurable regions, i.e. cache coherent sub-sections of a manycore architecture. In this paper, a technique for supporting the regionbased cache coherence mechanism by using so called in-NoC circuits (INCs) in a hybrid networks-on-chip is proposed. These circuits are automatically established based on traffic monitoring and traffic analysis to connect nodes (i.e. routers) in the network to enable a shortcut for packets, reducing their latency. The INCs can be used by packets stemming from different sources and targeting different destinations in contrast to traditional end-toend circuits. Depending on the coherence region, our evaluations of several benchmarks show a latency reduction of up to 45% on average in a 4x4 mesh that further increases with the mesh size. The FPGA synthesis of a router from a scientific DSM architecture that was extended with the presented features shows additional costs of up to 31% more LUTs and 20% more Flip Flops.