Implementation of a transaction level assertion framework in systemC

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

45 Scopus citations

Abstract

Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling.

Original languageEnglish
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Pages894-899
Number of pages6
DOIs
StatePublished - 2007
Externally publishedYes
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: 16 Apr 200720 Apr 2007

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference2007 Design, Automation and Test in Europe Conference and Exhibition
Country/TerritoryFrance
CityNice Acropolis
Period16/04/0720/04/07

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