Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis

The ratio of wire capacitances to gate input capacitances is an important parameter affecting power optimization through dual supply voltage scaling (DSVS) and gate resizing (GR). Nevertheless, it was disregarded in all previous work. In this paper, an increase in the said capacitance ratio in future technology generations is projected from different device and interconnect scaling roadmaps. A power-driven logic synthesis methodology, which enables DSVS in addition to GR, has been applied to MCNC benchmark circuits subject to a varying ratio of the said capacitances. The results show that, if both techniques are applied simultaneously, the power reduction that can be achieved through GR decreases noticeably as wire capacitances become more dominant. At the same time, the effect of DSVS tends to increase slightly. Thus, DSVS can be considered a power optimization technique of growing importance.