Impact of level-converter on power-saving capability of clustered voltage scaling

The use of multiple supply voltages to reduce active mode power dissipation in digital ULSI circuits has been widely discussed in literature. As the reported power savings differ significantly depending on the technology and level converter circuits an abstract approach is used to investigate the impact of power consumption and delay caused by the level converters (what-if-scenarios). Actual circuits are used to map the theoretical investigations to real circuits. In contrast to clustered voltage scaling, where level conversion is only allowed in front of or within flipflops the power saving benefits of enhanced clustered voltage scaling with arbitrary converter positions vanish due to the lack of efficient asynchronous level converters.