III-V-on-CMOS Devices and Circuits: Opportunities in Quantum Infrastructure

C. B. Zota, T. Morf, P. Muller, C. Convertino, S. Filipp, W. Riess, L. Czornomaz

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

In this work, we present a sequentially 3D integrated III-V-on-CMOS RF MOSFET technology with state-of-the-art RF performance. This platform is particularly promising for cryogenic applications where cooling power and space is limited, as the III-V devices offer reduced power dissipation while the 3D architecture enables small form-factors and reduced latencies. The unique features of III-V materials also enable novel devices. Here, we propose and show key experimental results of a quantized LNA, a cryogenic III-V nanowire amplifier that can significantly outperform standard HEMT technology. As heat dissipation is a key limitation in 3D architectures, we explore self-heating effects in CMOS using integrated temperature sensors. These results show the promise of III-V-on-CMOS for cryogenic applications such as integrated electronics for HPC, quantum computing and space.

Original languageEnglish
Title of host publication2019 IEEE International Electron Devices Meeting, IEDM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728140315
DOIs
StatePublished - Dec 2019
Externally publishedYes
Event65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
Duration: 7 Dec 201911 Dec 2019

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2019-December
ISSN (Print)0163-1918

Conference

Conference65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country/TerritoryUnited States
CitySan Francisco
Period7/12/1911/12/19

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