@inproceedings{d1f69ad771d84baa8830fa80781e8d6d,
title = "HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner",
abstract = "Hypergraph partitioning plays a critical role in computer-aided design (CAD) because it allows us to break down a large circuit into several manageable pieces that facilitate efficient CAD algorithm designs. However, as circuit designs continue to grow in size, hypergraph partitioning becomes increasingly time-consuming. Recent research has introduced parallel hypergraph partitioners using multi-core CPUs to reduce the long runtime. However, the speedup of existing CPU parallel hypergraph partitioners is typically limited to a few cores. To overcome these challenges, we propose HyperG, a GPU-accelerated multilevel k-way hypergraph partitioning algorithm. HyperG introduces an innovative balanced group coarsening and a sequence-based refinement algorithm to accelerate both the coarsening and uncoarsening stages. Experimental results show that HyperG outperforms both the state-of-the-art sequential and CPU-based parallel partitioners with an average speedup of 133× and 4.1× while achieving comparable partitioning quality.",
author = "Lee, {Wan Luan} and Lin, {Dian Lun} and Chiu, {Cheng Hsiang} and Ulf Schlichtmann and Huang, {Tsung Wei}",
note = "Publisher Copyright: {\textcopyright} 2025 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.; 30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025 ; Conference date: 20-01-2025 Through 23-01-2025",
year = "2025",
month = mar,
day = "4",
doi = "10.1145/3658617.3697551",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1031--1040",
booktitle = "ASP-DAC 2025 - 30th Asia and South Pacific Design Automation Conference, Proceedings",
}