HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner

Wan Luan Lee, Dian Lun Lin, Cheng Hsiang Chiu, Ulf Schlichtmann, Tsung Wei Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Hypergraph partitioning plays a critical role in computer-aided design (CAD) because it allows us to break down a large circuit into several manageable pieces that facilitate efficient CAD algorithm designs. However, as circuit designs continue to grow in size, hypergraph partitioning becomes increasingly time-consuming. Recent research has introduced parallel hypergraph partitioners using multi-core CPUs to reduce the long runtime. However, the speedup of existing CPU parallel hypergraph partitioners is typically limited to a few cores. To overcome these challenges, we propose HyperG, a GPU-accelerated multilevel k-way hypergraph partitioning algorithm. HyperG introduces an innovative balanced group coarsening and a sequence-based refinement algorithm to accelerate both the coarsening and uncoarsening stages. Experimental results show that HyperG outperforms both the state-of-the-art sequential and CPU-based parallel partitioners with an average speedup of 133× and 4.1× while achieving comparable partitioning quality.

Original languageEnglish
Title of host publicationASP-DAC 2025 - 30th Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1031-1040
Number of pages10
ISBN (Electronic)9798400706356
DOIs
StatePublished - 4 Mar 2025
Event30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025 - Tokyo, Japan
Duration: 20 Jan 202523 Jan 2025

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ISSN (Print)2153-6961
ISSN (Electronic)2153-697X

Conference

Conference30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025
Country/TerritoryJapan
CityTokyo
Period20/01/2523/01/25

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