HW/SW Codesign for Approximate In-Memory Computing

Innovations in Artificial Intelligence (AI) algorithms are rapidly reshaping our world and daily life. However, Deep Neural Networks (DNNs), which are the heart of many AI algorithms, impose profound challenges when they are being executed on top of the existing computer architectures. As a matter of fact, the massive amount of data, that DNNs demand, overwhelms the existing von-Neumann architecture because the latter is fundamentally bottlenecked by the data movement between the physically-separated processing elements and memory blocks. Therefore, there is, more than ever before, a relentless increase in the need for breakthroughs at both hardware and software sides in order to bring AI to the next level. Nevertheless, such breakthroughs would indispensably necessitate novel and elegant HW/SW codesign methodologies towards maximizing the accuracy without scarifying the gained efficiency. In this work, we focus on how Ternary Content Addressable Memory (TCAM) circuits, that perform approximate in-memory Hamming distance computing, can be realized using both classical CMOS-based SRAM memories and emerging beyond-CMOS Ferroelectric FET (FeFET) non-volatile memories. Further, we demonstrate how HS/SW codesign allows an outstanding synergy between brain-inspired Hyperdimensional Computing (HDC) and novel beyond-von Neumann architectures towards realizing ultra-efficient, yet accurate machine learning algorithms.