Hot-spot aware thermoelectric array based cooling for multicore processors

In this paper, we propose a hot-spot aware Thermoelectric Cooler (TEC)-based active cooling technique, called TEC-Array, which can perform targeted cooling of the spatially and temporally changing on-chip hot spots in any multi-core processor. It is in contrast to many existing works, where TECs were used for spatially homogeneous cooling, which leads to high energy costs. The proposed cooling system involves a 2D array of TEC modules where each TEC module is individually controllable. This enables the ability to spatially vary the cooling for hot spots across the chip's surface while the processor is under load. This way, the areas of the chip consuming more power, and consequently generating more heat, can be cooled more intensely than the areas that are consuming very little power. To dynamically control the TEC-Array, the proposed approach applies machine learning predicted full-chip power-density maps to generate discrete voltage maps which are in turn used to dynamically configure the voltage settings of the TEC-Array. In addition, we also propose a numerical simulation framework, which employs an accurate 3D coupled multi-physics model for TEC devices to consider Peltier, heat transfer, Joule heating and complex electro-thermal coupling effects by solving the coupled heat conduction and current continuity equations. The numerical results on an Intel quad-core chip shows that the proposed TEC-Array cooling can substantially reduce the peak temperatures compared to the traditional passive heat sink cooling method. Furthermore, compared to the existing single TEC module based cooling method, the proposed method can reduce both TEC power and temperature gradients across chips under the same maximum temperature constraints, which can further reduce spatial temperature induced stress such as thermal cycling, thermo-migration and unbalanced aging etc. As a result, the new TEC-Array cooling can enable more aggressive chip performance with increased thermal design power (TDP) while maintaining the chip design lifetime.