High abstraction level permutational ESD concept analysis

M. Streibl; F. Zängl; K. Esmark; R. Schwencker; W. Stadler; H. Gossner; S. Drüen; D. Schmitt-Landsiedel

doi:10.1016/j.microrel.2004.05.019

High abstraction level permutational ESD concept analysis

M. Streibl, F. Zängl, K. Esmark, R. Schwencker, W. Stadler, H. Gossner, S. Drüen, D. Schmitt-Landsiedel

Medicine and Health

Research output: Contribution to journal › Article › peer-review

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Abstract

A simulation approach is presented that allows handling ESD simulation and analysis on a chip-level complexity. In a Monte-Carlo like permutational simulation approach, worst case ESD paths are identified. The simulator is embedded in an ESD analysis framework spanning from the chip protection description to an automated virtual HBM test routine with a respective fail reporting interface. The tools capabilities are demonstrated in the ESD analysis of a complex mixed-signal design.

Original language	English
Pages (from-to)	313-321
Number of pages	9
Journal	Microelectronics Reliability
Volume	45
Issue number	2
DOIs	https://doi.org/10.1016/j.microrel.2004.05.019
State	Published - Feb 2005

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10.1016/j.microrel.2004.05.019

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AU - Esmark, K.

AU - Schwencker, R.

AU - Stadler, W.

AU - Gossner, H.

AU - Drüen, S.

AU - Schmitt-Landsiedel, D.

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AB - A simulation approach is presented that allows handling ESD simulation and analysis on a chip-level complexity. In a Monte-Carlo like permutational simulation approach, worst case ESD paths are identified. The simulator is embedded in an ESD analysis framework spanning from the chip protection description to an automated virtual HBM test routine with a respective fail reporting interface. The tools capabilities are demonstrated in the ESD analysis of a complex mixed-signal design.

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High abstraction level permutational ESD concept analysis

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