TY - GEN
T1 - Hierarchical synthesis of reversible circuits using positive and negative davio decomposition
AU - Soeken, Mathias
AU - Wille, Robert
AU - Drechsler, Rolf
PY - 2010
Y1 - 2010
N2 - Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology. Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decomposition. However, this approach leads to circuits with high costs. In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition. We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits. Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32%. In the best case, even reductions of more than 60% are possible.
AB - Synthesis of reversible circuits is an important research area providing the basis for a design flow of this emerging technology. Recently, in the development of scalable synthesis approaches a significant step forward has been made by a hierarchical method in combination with Shannon decomposition. However, this approach leads to circuits with high costs. In this paper, we propose an alternative that additionally makes use of positive Davio and negative Davio decomposition. We show that the usage of these decomposition types offers several advantages for the synthesis of reversible circuits. Using the proposed approach, on average the number of lines can be reduced by 22%, the number of gates by 22%, and the quantum cost by 32%. In the best case, even reductions of more than 60% are possible.
UR - http://www.scopus.com/inward/record.url?scp=79953071841&partnerID=8YFLogxK
U2 - 10.1109/IDT.2010.5724427
DO - 10.1109/IDT.2010.5724427
M3 - Conference contribution
AN - SCOPUS:79953071841
SN - 9781612842929
T3 - IDT'10 - 2010 5th International Design and Test Workshop, Proceedings
SP - 143
EP - 148
BT - IDT'10 - 2010 5th International Design and Test Workshop, Proceedings
T2 - 2010 5th International Design and Test Workshop, IDT'10
Y2 - 14 December 2010 through 15 December 2010
ER -