Hierarchical architecture for fast CMOS SRAMs

D. Schmitt-Landsiedel; G. Neuendorf; B. Hoppe; H. J. Mattausch

Hierarchical architecture for fast CMOS SRAMs

D. Schmitt-Landsiedel, G. Neuendorf, B. Hoppe, H. J. Mattausch

Siemens AG

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1-μm technology yield a 9-ns access time for a 64K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage.

Original language	English
Title of host publication	VLSI and Computer Peripherals
Editors	Walter E. Proebster, Hans Reiner, W. Schilz, C. Butterworth, E. Lueder, al et al
Publisher	Publ by IEEE
Pages	1/32-34
ISBN (Print)	0818619406
State	Published - 1989
Externally published	Yes
Event	COMPEURO '89 - 3rd Annual European Computer Conference - Hamburg, West Ger Duration: 8 May 1989 → 12 May 1989

Publication series

Name	VLSI and Computer Peripherals

Conference

Conference	COMPEURO '89 - 3rd Annual European Computer Conference
City	Hamburg, West Ger
Period	8/05/89 → 12/05/89

Cite this

@inproceedings{170b075d7c764902a24be45b0a24c616,

title = "Hierarchical architecture for fast CMOS SRAMs",

abstract = "A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1-μm technology yield a 9-ns access time for a 64K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage.",

author = "D. Schmitt-Landsiedel and G. Neuendorf and B. Hoppe and Mattausch, {H. J.}",

year = "1989",

language = "English",

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series = "VLSI and Computer Peripherals",

publisher = "Publ by IEEE",

pages = "1/32--34",

editor = "Proebster, {Walter E.} and Hans Reiner and W. Schilz and C. Butterworth and E. Lueder and {et al}, al",

booktitle = "VLSI and Computer Peripherals",

note = "COMPEURO '89 - 3rd Annual European Computer Conference ; Conference date: 08-05-1989 Through 12-05-1989",

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Hierarchical architecture for fast CMOS SRAMs. / Schmitt-Landsiedel, D.; Neuendorf, G.; Hoppe, B. et al.
VLSI and Computer Peripherals. ed. / Walter E. Proebster; Hans Reiner; W. Schilz; C. Butterworth; E. Lueder; al et al. Publ by IEEE, 1989. p. 1/32-34 (VLSI and Computer Peripherals).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Hierarchical architecture for fast CMOS SRAMs

AU - Schmitt-Landsiedel, D.

AU - Neuendorf, G.

AU - Hoppe, B.

AU - Mattausch, H. J.

PY - 1989

Y1 - 1989

N2 - A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1-μm technology yield a 9-ns access time for a 64K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage.

AB - A new concept for the design of fast SRAMs is described, introducing a highly hierarchical architecture with short word and bit lines. Computational results based on layouts in a standard 1-μm technology yield a 9-ns access time for a 64K SRAM. The authors estimate that the access time is at least 50% longer in a conventional architecture, while the area is about 30% smaller. No address transition detection circuitry or other internal timing is required for the hierarchical approach. No critical analog circuit parts are applied. The new concept shows little sensitivity with respect to technology variations and can also be used for future technology generations with reduced supply voltage.

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M3 - Conference contribution

AN - SCOPUS:0024902523

SN - 0818619406

T3 - VLSI and Computer Peripherals

SP - 1/32-34

BT - VLSI and Computer Peripherals

A2 - Proebster, Walter E.

A2 - Reiner, Hans

A2 - Schilz, W.

A2 - Butterworth, C.

A2 - Lueder, E.

A2 - et al, al

PB - Publ by IEEE

T2 - COMPEURO '89 - 3rd Annual European Computer Conference

Y2 - 8 May 1989 through 12 May 1989

ER -

Hierarchical architecture for fast CMOS SRAMs

Abstract

Publication series

Conference

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