TY - GEN
T1 - Generic Error Localization for the Electronic System Level
AU - Pointner, Sebastian
AU - De Aledo, Pablo González
AU - Wille, Robert
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - Several methods and tools have been proposed which supports designers in verifying embedded systems in early phases of the design process, e.g. at the Electronic System Level (ESL). However, they only show whether an error indeed exists in the system, but it frequently remains open to efficiently locate the source of this error. In this work, we propose a generic error localization methodology. More precisely, by applying code augmentations and conducting further runs of the verification method, it is analyzed what statements may have caused the error. The respectively determined statements then pin-point the verification engineer to possible error locations. By conducing all this on the code level only, the proposed methodology can be applied to any verification method available today. The suitability of the proposed methodology is demonstrated by means of a verification flow based on symbolic execution.
AB - Several methods and tools have been proposed which supports designers in verifying embedded systems in early phases of the design process, e.g. at the Electronic System Level (ESL). However, they only show whether an error indeed exists in the system, but it frequently remains open to efficiently locate the source of this error. In this work, we propose a generic error localization methodology. More precisely, by applying code augmentations and conducting further runs of the verification method, it is analyzed what statements may have caused the error. The respectively determined statements then pin-point the verification engineer to possible error locations. By conducing all this on the code level only, the proposed methodology can be applied to any verification method available today. The suitability of the proposed methodology is demonstrated by means of a verification flow based on symbolic execution.
UR - http://www.scopus.com/inward/record.url?scp=85067570511&partnerID=8YFLogxK
U2 - 10.1109/DDECS.2019.8724637
DO - 10.1109/DDECS.2019.8724637
M3 - Conference contribution
AN - SCOPUS:85067570511
T3 - Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
BT - Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
Y2 - 24 April 2019 through 26 April 2019
ER -