Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation

The development of chip generators instead of the development of individual chips is an important trend in digital design that is picking up momentum both in academia and industry. The reuse of IP generators has significant potential to increase productivity as the generators can be rerun without manual design work to generate different IPs, optimized for different applications and trade-off criteria. Two key limiting factors for the reuse of IP generators are the need to develop individual IP generators with SoC integration aspects in mind and the need for SoC generators to handle IP integration aspects of different generated IPs. This work proposes a generator architecture based on best-practice software architectural patterns that address these limitations. The proposed architecture allows IP generators to be developed independently from SoC integration aspects and enables communication and collaboration between generators to align on a common, optimal architecture. This also enables the development of SoC infrastructure generators that automatically generate suitable SoC infrastructure based on the information collected from the individual IP generators. The suggested architecture significantly simplifies the task of top-level integration and guarantees that existing generators can be reused in SoC contexts with different infrastructure properties.