Generation of hardware machine models from instruction set descriptions

A. Fauth; M. Freericks; A. Knoll

doi:10.1109/VLSISP.1993.404482

Generation of hardware machine models from instruction set descriptions

A. Fauth, M. Freericks, A. Knoll

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

16 Scopus citations

Abstract

The authors describe how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from new generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example.

Original language	English
Title of host publication	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	242-250
Number of pages	9
ISBN (Electronic)	0780309960, 9780780309968
DOIs	https://doi.org/10.1109/VLSISP.1993.404482
State	Published - 1993
Externally published	Yes
Event	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 - Veldhoven, Netherlands Duration: 20 Oct 1993 → 22 Oct 1993

Publication series

Name	Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993
Country/Territory	Netherlands
City	Veldhoven
Period	20/10/93 → 22/10/93

Access to Document

10.1109/VLSISP.1993.404482

Cite this

Fauth, A., Freericks, M., & Knoll, A. (1993). Generation of hardware machine models from instruction set descriptions. In Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993 (pp. 242-250). Article 404482 (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1993.404482

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title = "Generation of hardware machine models from instruction set descriptions",

abstract = "The authors describe how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from new generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example.",

author = "A. Fauth and M. Freericks and A. Knoll",

note = "Publisher Copyright: {\textcopyright} 1993 IEEE.; 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993 ; Conference date: 20-10-1993 Through 22-10-1993",

year = "1993",

doi = "10.1109/VLSISP.1993.404482",

language = "English",

series = "Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "242--250",

booktitle = "Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993",

}

Fauth, A, Freericks, M & Knoll, A 1993, Generation of hardware machine models from instruction set descriptions. in Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993., 404482, Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993, Institute of Electrical and Electronics Engineers Inc., pp. 242-250, 6th IEEE Workshop on VLSI Signal Processing, VLSISP 1993, Veldhoven, Netherlands, 20/10/93. https://doi.org/10.1109/VLSISP.1993.404482

Generation of hardware machine models from instruction set descriptions. / Fauth, A.; Freericks, M.; Knoll, A.
Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993. Institute of Electrical and Electronics Engineers Inc., 1993. p. 242-250 404482 (Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The authors describe how a modular machine description, which specifies the functionality and the binary representation of an instruction set, can be transformed into a hardware model. This model is built from new generic hardware entities (registers, memories, arithmetic/logic operators, selectors and connections) and may eventually serve as an input to high-level hardware synthesis tools. The transformation steps on the way from the machine description to the hardware model are explained by giving an example.

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ER -

Generation of hardware machine models from instruction set descriptions

Abstract

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