Generalized rate analysis for media-processing platforms

In this paper we address the "rate analysis" problem for media-processing platforms consisting of multiple processor cores connected in a pipelined fashion. More precisely, we aim at determining tight bounds on the rates at which multimedia streams can be fed into such urchitectures. These bounds depend on architectural constraints (e.g. the available on-chip memory, bus arbitration policies, etc.), as well as the application characteristics (e.g. application partitioning and mapping, workload rates generated by different tasks, etc.). The proposed framework for rate analysis can be used for fast design space exploration to determine how these bounds change with different architectural parameters, mapping of the application, or changing the QoS requirements associated with the input streams.