Gate-level-accurate fault-effect analysis at virtual-prototype speed

Bogdan Andrei Tabacaru; Moomen Chaari; Wolfgang Ecker; Thomas Kruse; Cristiano Novello

doi:10.1007/978-3-319-45480-1_12

Gate-level-accurate fault-effect analysis at virtual-prototype speed

Bogdan Andrei Tabacaru
, Moomen Chaari
, Wolfgang Ecker
, Thomas Kruse
, Cristiano Novello

Computation, Information and Technology

Infineon Technologies AG
Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The cost of efficient fault-effect analysis on gate-level (GL) and register-transfer level models is increasing due to the rising complexity of safety-critical systems on chip (SoCs). Virtual prototypes (VPs) based on transaction-level models are employed to speed-up safety verification. However, VP structures correlate poorly to GL models. This leads to the injection of pseudo-faults into VPs and to the development of suboptimal safety mechanisms for the SoC. To mitigate these drawbacks, in this paper, we propose a safety-verification flow for VPs to maintain 100% correlation to GL models and to ensure the injection of realistic faults into VPs. Our approach’s key aspects are: matching points across abstraction levels and selective abstraction of GL functionality using compiled-code simulation. Measurements show two orders of magnitude speed-up over RTL models and three orders of magnitude over GL models. Moreover, the speed-up increases with design size.

Original language	English
Title of host publication	Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings
Editors	Jérémie Guiochet, Erwin Schoitsch, Friedemann Bitsch, Amund Skavhaug
Publisher	Springer Verlag
Pages	144-156
Number of pages	13
ISBN (Print)	9783319454795
DOIs	https://doi.org/10.1007/978-3-319-45480-1_12
State	Published - 2016
Event	International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2016 and International Workshop on Assurance Cases for Software-Intensive Systems, ASSURE 2016, Workshop on Dependable Embedded and Cyber-physical Systems and Systems-of-Systems, DECSoS 2016, 5th International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems, SASSUR 2016, and 1st International Workshop on the Timing Performance in Safety Engineering, TIPS 2016 - Trondheim, Norway Duration: 21 Sep 2016 → 23 Sep 2016

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	9923 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2016 and International Workshop on Assurance Cases for Software-Intensive Systems, ASSURE 2016, Workshop on Dependable Embedded and Cyber-physical Systems and Systems-of-Systems, DECSoS 2016, 5th International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems, SASSUR 2016, and 1st International Workshop on the Timing Performance in Safety Engineering, TIPS 2016
Country/Territory	Norway
City	Trondheim
Period	21/09/16 → 23/09/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy
SDG 9 Industry, Innovation, and Infrastructure
SDG 12 Responsible Consumption and Production

Keywords

Automotive
Fault injection
ISO 26262
Safety verification
SystemC
TLM
Virtual prototyping

Access to Document

10.1007/978-3-319-45480-1_12

Cite this

Tabacaru, B. A., Chaari, M., Ecker, W., Kruse, T., & Novello, C. (2016). Gate-level-accurate fault-effect analysis at virtual-prototype speed. In J. Guiochet, E. Schoitsch, F. Bitsch, & A. Skavhaug (Eds.), Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings (pp. 144-156). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 9923 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-319-45480-1_12

Tabacaru, Bogdan Andrei ; Chaari, Moomen ; Ecker, Wolfgang et al. / Gate-level-accurate fault-effect analysis at virtual-prototype speed. Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings. editor / Jérémie Guiochet ; Erwin Schoitsch ; Friedemann Bitsch ; Amund Skavhaug. Springer Verlag, 2016. pp. 144-156 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "The cost of efficient fault-effect analysis on gate-level (GL) and register-transfer level models is increasing due to the rising complexity of safety-critical systems on chip (SoCs). Virtual prototypes (VPs) based on transaction-level models are employed to speed-up safety verification. However, VP structures correlate poorly to GL models. This leads to the injection of pseudo-faults into VPs and to the development of suboptimal safety mechanisms for the SoC. To mitigate these drawbacks, in this paper, we propose a safety-verification flow for VPs to maintain 100\% correlation to GL models and to ensure the injection of realistic faults into VPs. Our approach{\textquoteright}s key aspects are: matching points across abstraction levels and selective abstraction of GL functionality using compiled-code simulation. Measurements show two orders of magnitude speed-up over RTL models and three orders of magnitude over GL models. Moreover, the speed-up increases with design size.",

keywords = "Automotive, Fault injection, ISO 26262, Safety verification, SystemC, TLM, Virtual prototyping",

author = "Tabacaru, \{Bogdan Andrei\} and Moomen Chaari and Wolfgang Ecker and Thomas Kruse and Cristiano Novello",

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booktitle = "Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings",

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Tabacaru, BA, Chaari, M, Ecker, W, Kruse, T & Novello, C 2016, Gate-level-accurate fault-effect analysis at virtual-prototype speed. in J Guiochet, E Schoitsch, F Bitsch & A Skavhaug (eds), Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 9923 LNCS, Springer Verlag, pp. 144-156, International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2016 and International Workshop on Assurance Cases for Software-Intensive Systems, ASSURE 2016, Workshop on Dependable Embedded and Cyber-physical Systems and Systems-of-Systems, DECSoS 2016, 5th International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems, SASSUR 2016, and 1st International Workshop on the Timing Performance in Safety Engineering, TIPS 2016, Trondheim, Norway, 21/09/16. https://doi.org/10.1007/978-3-319-45480-1_12

Gate-level-accurate fault-effect analysis at virtual-prototype speed. / Tabacaru, Bogdan Andrei; Chaari, Moomen; Ecker, Wolfgang et al.
Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings. ed. / Jérémie Guiochet; Erwin Schoitsch; Friedemann Bitsch; Amund Skavhaug. Springer Verlag, 2016. p. 144-156 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 9923 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Gate-level-accurate fault-effect analysis at virtual-prototype speed

AU - Tabacaru, Bogdan Andrei

AU - Chaari, Moomen

AU - Ecker, Wolfgang

AU - Kruse, Thomas

AU - Novello, Cristiano

N1 - Publisher Copyright: © Springer International Publishing Switzerland 2016.

PY - 2016

Y1 - 2016

N2 - The cost of efficient fault-effect analysis on gate-level (GL) and register-transfer level models is increasing due to the rising complexity of safety-critical systems on chip (SoCs). Virtual prototypes (VPs) based on transaction-level models are employed to speed-up safety verification. However, VP structures correlate poorly to GL models. This leads to the injection of pseudo-faults into VPs and to the development of suboptimal safety mechanisms for the SoC. To mitigate these drawbacks, in this paper, we propose a safety-verification flow for VPs to maintain 100% correlation to GL models and to ensure the injection of realistic faults into VPs. Our approach’s key aspects are: matching points across abstraction levels and selective abstraction of GL functionality using compiled-code simulation. Measurements show two orders of magnitude speed-up over RTL models and three orders of magnitude over GL models. Moreover, the speed-up increases with design size.

AB - The cost of efficient fault-effect analysis on gate-level (GL) and register-transfer level models is increasing due to the rising complexity of safety-critical systems on chip (SoCs). Virtual prototypes (VPs) based on transaction-level models are employed to speed-up safety verification. However, VP structures correlate poorly to GL models. This leads to the injection of pseudo-faults into VPs and to the development of suboptimal safety mechanisms for the SoC. To mitigate these drawbacks, in this paper, we propose a safety-verification flow for VPs to maintain 100% correlation to GL models and to ensure the injection of realistic faults into VPs. Our approach’s key aspects are: matching points across abstraction levels and selective abstraction of GL functionality using compiled-code simulation. Measurements show two orders of magnitude speed-up over RTL models and three orders of magnitude over GL models. Moreover, the speed-up increases with design size.

KW - Automotive

KW - Fault injection

KW - ISO 26262

KW - Safety verification

KW - SystemC

KW - TLM

KW - Virtual prototyping

UR - https://www.scopus.com/pages/publications/84988419419

U2 - 10.1007/978-3-319-45480-1_12

DO - 10.1007/978-3-319-45480-1_12

M3 - Conference contribution

AN - SCOPUS:84988419419

SN - 9783319454795

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 144

EP - 156

BT - Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings

A2 - Guiochet, Jérémie

A2 - Schoitsch, Erwin

A2 - Bitsch, Friedemann

A2 - Skavhaug, Amund

PB - Springer Verlag

T2 - International Conference on Computer Safety, Reliability, and Security, SAFECOMP 2016 and International Workshop on Assurance Cases for Software-Intensive Systems, ASSURE 2016, Workshop on Dependable Embedded and Cyber-physical Systems and Systems-of-Systems, DECSoS 2016, 5th International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems, SASSUR 2016, and 1st International Workshop on the Timing Performance in Safety Engineering, TIPS 2016

Y2 - 21 September 2016 through 23 September 2016

ER -

Tabacaru BA, Chaari M, Ecker W, Kruse T, Novello C. Gate-level-accurate fault-effect analysis at virtual-prototype speed. In Guiochet J, Schoitsch E, Bitsch F, Skavhaug A, editors, Computer Safety, Reliability, and Security, SAFECOMP 2016 - Workshops ASSURE, DECSoS, SASSUR, and TIPS, Proceedings. Springer Verlag. 2016. p. 144-156. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-319-45480-1_12

Gate-level-accurate fault-effect analysis at virtual-prototype speed

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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