Fully scalable gain memory cell for future drams

W. H. Krautschneider; L. Risch; K. Lau; D. Schmitt-Landsiedel

doi:10.1016/0167-9317(91)90246-A

Fully scalable gain memory cell for future drams

W. H. Krautschneider
, L. Risch
, K. Lau
, D. Schmitt-Landsiedel

Research output: Contribution to journal › Article › peer-review

Abstract

A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.

Original language	English
Pages (from-to)	367-370
Number of pages	4
Journal	Microelectronic Engineering
Volume	15
Issue number	1-4
DOIs	https://doi.org/10.1016/0167-9317(91)90246-A
State	Published - Oct 1991
Externally published	Yes

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10.1016/0167-9317(91)90246-A

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@article{09465504625e457995c5ce882d644f08,

title = "Fully scalable gain memory cell for future drams",

abstract = "A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.",

author = "Krautschneider, \{W. H.\} and L. Risch and K. Lau and D. Schmitt-Landsiedel",

year = "1991",

month = oct,

doi = "10.1016/0167-9317(91)90246-A",

language = "English",

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T1 - Fully scalable gain memory cell for future drams

AU - Krautschneider, W. H.

AU - Risch, L.

AU - Lau, K.

AU - Schmitt-Landsiedel, D.

PY - 1991/10

Y1 - 1991/10

N2 - A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.

AB - A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.

UR - https://www.scopus.com/pages/publications/0026238328

U2 - 10.1016/0167-9317(91)90246-A

DO - 10.1016/0167-9317(91)90246-A

M3 - Article

AN - SCOPUS:0026238328

SN - 0167-9317

VL - 15

SP - 367

EP - 370

JO - Microelectronic Engineering

JF - Microelectronic Engineering

IS - 1-4

ER -

Fully scalable gain memory cell for future drams

Abstract

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