Fully scalable gain memory cell for future drams

W. H. Krautschneider, L. Risch, K. Lau, D. Schmitt-Landsiedel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.

Original languageEnglish
Title of host publicationEuropean Solid-State Device Research Conference
EditorsM. Ilegems, M. Dutoit
PublisherIEEE Computer Society
Pages367-370
Number of pages4
ISBN (Electronic)0444890661
StatePublished - 1991
Externally publishedYes
Event21st European Solid State Device Research Conference, ESSDERC 1991 - Montreux, Switzerland
Duration: 16 Sep 199119 Sep 1991

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference21st European Solid State Device Research Conference, ESSDERC 1991
Country/TerritorySwitzerland
CityMontreux
Period16/09/9119/09/91

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