TY - GEN
T1 - Fully FPGA based performance-enhanced DMPC for grid-tied AFEs with multiple predictions
AU - Zhang, Zhenbin
AU - Chen, Zhe
AU - Wang, Fengxiang
AU - Wu, Chun
AU - Kennel, Ralph
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015
Y1 - 2015
N2 - Direct Model Predictive Control (DMPC) is an attractive control method for power electronics and drives, characterized by straightforward concept, nice dynamics and great flexibility. However, relatively big ripples of the control variables and heavy computational efforts are regarded as two of the shortcomings. To cope with these, this work proposes a performance-enhanced DMPC concept with multi-predictions and lower computational efforts. The novelty of the proposed scheme is two-folds: i) By dividing each sampling interval into 3 prediction periods, the resolution of the control accuracy is therefore improved compared with the classical DMPC schemes with the same sampling period; ii) Instead of using the exhausting enumeration concept, a deadbeat notion is in-cooperated to find the equivalently optimal vectors and much lower computational efforts are therefore required. As a case of study it is here verified on a grid-tied two level Active-Front-End (AFE) and is realized using an entirely FPGA based solution. Compared with the classical DMPC schemes, better current/power qualities are achieved with the same sampling frequency. The effectiveness of the proposed scheme is emphasized with experimental results.
AB - Direct Model Predictive Control (DMPC) is an attractive control method for power electronics and drives, characterized by straightforward concept, nice dynamics and great flexibility. However, relatively big ripples of the control variables and heavy computational efforts are regarded as two of the shortcomings. To cope with these, this work proposes a performance-enhanced DMPC concept with multi-predictions and lower computational efforts. The novelty of the proposed scheme is two-folds: i) By dividing each sampling interval into 3 prediction periods, the resolution of the control accuracy is therefore improved compared with the classical DMPC schemes with the same sampling period; ii) Instead of using the exhausting enumeration concept, a deadbeat notion is in-cooperated to find the equivalently optimal vectors and much lower computational efforts are therefore required. As a case of study it is here verified on a grid-tied two level Active-Front-End (AFE) and is realized using an entirely FPGA based solution. Compared with the classical DMPC schemes, better current/power qualities are achieved with the same sampling frequency. The effectiveness of the proposed scheme is emphasized with experimental results.
KW - Computationally Efficient DMPC
KW - FPGA Digital Controller Design
KW - Grid-Tied AFE
KW - Multi-Prediction Per Sampling Interval
KW - Ripple-Reduced DMPC
UR - http://www.scopus.com/inward/record.url?scp=84973143607&partnerID=8YFLogxK
U2 - 10.1109/IECON.2015.7392277
DO - 10.1109/IECON.2015.7392277
M3 - Conference contribution
AN - SCOPUS:84973143607
T3 - IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society
SP - 1282
EP - 1287
BT - IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015
Y2 - 9 November 2015 through 12 November 2015
ER -