Fully FPGA based performance-enhanced DMPC for grid-tied AFEs with multiple predictions

Zhenbin Zhang, Zhe Chen, Fengxiang Wang, Chun Wu, Ralph Kennel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Direct Model Predictive Control (DMPC) is an attractive control method for power electronics and drives, characterized by straightforward concept, nice dynamics and great flexibility. However, relatively big ripples of the control variables and heavy computational efforts are regarded as two of the shortcomings. To cope with these, this work proposes a performance-enhanced DMPC concept with multi-predictions and lower computational efforts. The novelty of the proposed scheme is two-folds: i) By dividing each sampling interval into 3 prediction periods, the resolution of the control accuracy is therefore improved compared with the classical DMPC schemes with the same sampling period; ii) Instead of using the exhausting enumeration concept, a deadbeat notion is in-cooperated to find the equivalently optimal vectors and much lower computational efforts are therefore required. As a case of study it is here verified on a grid-tied two level Active-Front-End (AFE) and is realized using an entirely FPGA based solution. Compared with the classical DMPC schemes, better current/power qualities are achieved with the same sampling frequency. The effectiveness of the proposed scheme is emphasized with experimental results.

Original languageEnglish
Title of host publicationIECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1282-1287
Number of pages6
ISBN (Electronic)9781479917624
DOIs
StatePublished - 2015
Event41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015 - Yokohama, Japan
Duration: 9 Nov 201512 Nov 2015

Publication series

NameIECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society

Conference

Conference41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015
Country/TerritoryJapan
CityYokohama
Period9/11/1512/11/15

Keywords

  • Computationally Efficient DMPC
  • FPGA Digital Controller Design
  • Grid-Tied AFE
  • Multi-Prediction Per Sampling Interval
  • Ripple-Reduced DMPC

Fingerprint

Dive into the research topics of 'Fully FPGA based performance-enhanced DMPC for grid-tied AFEs with multiple predictions'. Together they form a unique fingerprint.

Cite this