From roadmaps to reality: The challenges of designing tomorrow's chips

Heiner Herbst; Doris Schmitt-Landsiedel; Matthias Schöbinger

doi:10.1080/02564602.1996.11416630

From roadmaps to reality: The challenges of designing tomorrow's chips

Heiner Herbst
, Doris Schmitt-Landsiedel
, Matthias Schöbinger

Siemens AG

Research output: Contribution to journal › Article › peer-review

Abstract

Ever smaller structures and ever greater numbers of semiconductor elements on a single chip call for a growing level of interdisciplinary creativity among chip and system developers. Also required are measures designed to significantly reduce the power dissipation associated with each function, even as clock rates accelerate. As integration increases, another requirement is to integrate combinations of analog and digital circuits on a single chip.

Original language	English
Pages (from-to)	345-349
Number of pages	5
Journal	IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India)
Volume	13
Issue number	6
DOIs	https://doi.org/10.1080/02564602.1996.11416630
State	Published - 1996
Externally published	Yes

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10.1080/02564602.1996.11416630

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title = "From roadmaps to reality: The challenges of designing tomorrow's chips",

abstract = "Ever smaller structures and ever greater numbers of semiconductor elements on a single chip call for a growing level of interdisciplinary creativity among chip and system developers. Also required are measures designed to significantly reduce the power dissipation associated with each function, even as clock rates accelerate. As integration increases, another requirement is to integrate combinations of analog and digital circuits on a single chip.",

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year = "1996",

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AB - Ever smaller structures and ever greater numbers of semiconductor elements on a single chip call for a growing level of interdisciplinary creativity among chip and system developers. Also required are measures designed to significantly reduce the power dissipation associated with each function, even as clock rates accelerate. As integration increases, another requirement is to integrate combinations of analog and digital circuits on a single chip.

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M3 - Article

AN - SCOPUS:0030282999

SN - 0256-4602

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JO - IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India)

JF - IETE Technical Review (Institution of Electronics and Telecommunication Engineers, India)

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From roadmaps to reality: The challenges of designing tomorrow's chips

Abstract

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