TY - GEN
T1 - FPGA HiL simulation of back-to-back converter PMSG wind turbine systems
AU - Zhang, Zhenbin
AU - Wang, Fengxiang
AU - Acikgoz, Metehan
AU - Cai, Xinbo
AU - Kennel, Ralph
N1 - Publisher Copyright:
© 2015 Korean Institute of Power Electronics.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - This work presents a back-to-back power converter Permanent-magnet Synchronous Generator (PMSG) wind turbine real-time simulation system based on FPGA Hardware-in-the-Loop (HiL) concept. The proposed system can be used for Electric Control Units (ECUs) evaluation in a real-time manner. The refreshing rate effect of a HiL emulator is discussed and analyzed with real-time simulation proof. Within this work, per-unit system model of a 2MW Back-to-Back converter direct-drive PMSG wind turbine system is developed both in continuous and discrete formats. The effectiveness of the discrete per-unit system model is firstly verified through off-line simulation in Matlab/Simulink environment. Then by using a so-called Single-Cycle-Timed-Loop (SCTL) technique, the per-unit discrete system model is implemented on an FPGA based platform as the emulator, achieving a very high refreshing-rate (up to 250 kHz, i.e., 4μs). The emulator refreshing rate effect is evaluated in a real-time operating manner by implementing an ECU (using FOC/VOC control scheme) in a second FPGA chassis. At the end of this paper the results are analyzed and theoretically interpreted.
AB - This work presents a back-to-back power converter Permanent-magnet Synchronous Generator (PMSG) wind turbine real-time simulation system based on FPGA Hardware-in-the-Loop (HiL) concept. The proposed system can be used for Electric Control Units (ECUs) evaluation in a real-time manner. The refreshing rate effect of a HiL emulator is discussed and analyzed with real-time simulation proof. Within this work, per-unit system model of a 2MW Back-to-Back converter direct-drive PMSG wind turbine system is developed both in continuous and discrete formats. The effectiveness of the discrete per-unit system model is firstly verified through off-line simulation in Matlab/Simulink environment. Then by using a so-called Single-Cycle-Timed-Loop (SCTL) technique, the per-unit discrete system model is implemented on an FPGA based platform as the emulator, achieving a very high refreshing-rate (up to 250 kHz, i.e., 4μs). The emulator refreshing rate effect is evaluated in a real-time operating manner by implementing an ECU (using FOC/VOC control scheme) in a second FPGA chassis. At the end of this paper the results are analyzed and theoretically interpreted.
KW - Back-to-Back Power Converter
KW - FPGA Hardware-in-the-Loop Simulation
KW - PMSG
KW - Voltage and Field Oriented Control
KW - Wind Turbine System
UR - http://www.scopus.com/inward/record.url?scp=84961960747&partnerID=8YFLogxK
U2 - 10.1109/ICPE.2015.7167772
DO - 10.1109/ICPE.2015.7167772
M3 - Conference contribution
AN - SCOPUS:84961960747
T3 - 9th International Conference on Power Electronics - ECCE Asia: "Green World with Power Electronics", ICPE 2015-ECCE Asia
SP - 99
EP - 106
BT - 9th International Conference on Power Electronics - ECCE Asia
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th International Conference on Power Electronics - ECCE Asia, ICPE 2015-ECCE Asia
Y2 - 1 June 2015 through 5 June 2015
ER -