TY - GEN
T1 - FPGA based data read-out system of the Belle 2 pixel detector
AU - Levit, Dmytro
AU - Konorov, Igor
AU - Bai, Yunpeng
AU - Paul, Stephan
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/10/3
Y1 - 2016/10/3
N2 - The Belle 2 experiment is undergoing an upgrade with the aim to perform the most precise measurement of the CP-violation using the state-of-the-art detectors. The silicon pixel detector is the innermost layer of the experiment. Because of the increased beam background and the high detection efficiency of the silicon pixel detector, the data rate of the detector is estimated at 22 GB/s which is 10 times higher than the data rate of the remaining detectors in the experiment. We build a two stages FPGA-based data read-out system which controls the detector and prepares the data for the online data reduction. The system consists of 48 modules in AMC form factor which use Xilinx Virtex-6 FPGA and 4 GB DDR3 memory and 8 ATCA carrier boards with installed multi-channel cross-point switch for the dynamic interconnection of the FPGA modules. This setup enables the utilization of the hot spare modules which are activated in a case of module failure. The data processing in the system includes event re-assembly, cluster reconstruction and online sub-event building. To improve the quality of the data signal which is currently delivered over 15 m copper Infiniband cable, the radiation tolerance of the optical transmitters has been investigated. The paper will present the current system design and the results of the irradiation campaign.
AB - The Belle 2 experiment is undergoing an upgrade with the aim to perform the most precise measurement of the CP-violation using the state-of-the-art detectors. The silicon pixel detector is the innermost layer of the experiment. Because of the increased beam background and the high detection efficiency of the silicon pixel detector, the data rate of the detector is estimated at 22 GB/s which is 10 times higher than the data rate of the remaining detectors in the experiment. We build a two stages FPGA-based data read-out system which controls the detector and prepares the data for the online data reduction. The system consists of 48 modules in AMC form factor which use Xilinx Virtex-6 FPGA and 4 GB DDR3 memory and 8 ATCA carrier boards with installed multi-channel cross-point switch for the dynamic interconnection of the FPGA modules. This setup enables the utilization of the hot spare modules which are activated in a case of module failure. The data processing in the system includes event re-assembly, cluster reconstruction and online sub-event building. To improve the quality of the data signal which is currently delivered over 15 m copper Infiniband cable, the radiation tolerance of the optical transmitters has been investigated. The paper will present the current system design and the results of the irradiation campaign.
UR - http://www.scopus.com/inward/record.url?scp=84994187944&partnerID=8YFLogxK
U2 - 10.1109/NSSMIC.2015.7581845
DO - 10.1109/NSSMIC.2015.7581845
M3 - Conference contribution
AN - SCOPUS:84994187944
T3 - 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015
BT - 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015
Y2 - 31 October 2015 through 7 November 2015
ER -