TY - GEN
T1 - FPGA-based computation of free-form deformations
AU - Jiang, Jun
AU - Luk, W.
AU - Rueckert, D.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - This paper describes techniques for producing FPGA-based designs that support free-form deformation in medical image processing. The free-form deformation method is based on a B-spline algorithm for modelling three-dimensional deformable objects. Our design includes four optimisations. First, we store the values of a third-order B-spline model in lookup tables. Second, we adopt a customised number representation format in our implementation. Third, we transform a nested loop so that conditionals are moved outside the loop. Fourth, we pipeline the design to increase its throughput, and we also deploy multiple pipelines such that each covers a different image. Our design description, captured in the Handel-C language, is parameterisable at compile time to support a range of image resolutions and computational precisions. An implementation on a Xilinx XC2V6000 device would be capable of processing images of resolution up to 256 by 256 pixels in real time.
AB - This paper describes techniques for producing FPGA-based designs that support free-form deformation in medical image processing. The free-form deformation method is based on a B-spline algorithm for modelling three-dimensional deformable objects. Our design includes four optimisations. First, we store the values of a third-order B-spline model in lookup tables. Second, we adopt a customised number representation format in our implementation. Third, we transform a nested loop so that conditionals are moved outside the loop. Fourth, we pipeline the design to increase its throughput, and we also deploy multiple pipelines such that each covers a different image. Our design description, captured in the Handel-C language, is parameterisable at compile time to support a range of image resolutions and computational precisions. An implementation on a Xilinx XC2V6000 device would be capable of processing images of resolution up to 256 by 256 pixels in real time.
UR - http://www.scopus.com/inward/record.url?scp=84962803627&partnerID=8YFLogxK
U2 - 10.1109/FPT.2002.1188722
DO - 10.1109/FPT.2002.1188722
M3 - Conference contribution
AN - SCOPUS:84962803627
T3 - Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002
SP - 407
EP - 410
BT - Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1st IEEE International Conference on FieId-Programmable Technology, FPT 2002
Y2 - 16 December 2002 through 18 December 2002
ER -