TY - GEN
T1 - Formal specification level
AU - Drechsler, Rolf
AU - Soeken, Mathias
AU - Wille, Robert
PY - 2014
Y1 - 2014
N2 - The steadily increasing complexity of the design of embedded systems led to the development of both an elaborated design flow that includes various abstraction levels and corresponding methods for synthesis and verification. However, until today the initial system specification is provided in natural language which is manually translated into a formal implementation e.g. at the Electronic System Level (ESL) by means of SystemC in a time-consuming and error-prone process.In this chapter, we envision a design flow which incorporates a Formal Specification Level (FSL) aiming at bridging the gap between the informal textbook specification and the formal ESL implementation. Modeling languages such as UML or SysML are envisaged for this purpose. Recent accomplishments towards this envisioned design flow, namely the automatic derivation of formal models from natural language descriptions, verification of formal models in the absence of an implementation, and code generation techniques, are briefly reviewed.
AB - The steadily increasing complexity of the design of embedded systems led to the development of both an elaborated design flow that includes various abstraction levels and corresponding methods for synthesis and verification. However, until today the initial system specification is provided in natural language which is manually translated into a formal implementation e.g. at the Electronic System Level (ESL) by means of SystemC in a time-consuming and error-prone process.In this chapter, we envision a design flow which incorporates a Formal Specification Level (FSL) aiming at bridging the gap between the informal textbook specification and the formal ESL implementation. Modeling languages such as UML or SysML are envisaged for this purpose. Recent accomplishments towards this envisioned design flow, namely the automatic derivation of formal models from natural language descriptions, verification of formal models in the absence of an implementation, and code generation techniques, are briefly reviewed.
UR - http://www.scopus.com/inward/record.url?scp=84899729842&partnerID=8YFLogxK
U2 - 10.1007/978-3-319-01418-0_3
DO - 10.1007/978-3-319-01418-0_3
M3 - Conference contribution
AN - SCOPUS:84899729842
SN - 9783319014173
T3 - Lecture Notes in Electrical Engineering
SP - 37
EP - 52
BT - Models, Methods, and Tools for Complex Chip Design - Selected Contributions from FDL 2012
PB - Springer Verlag
T2 - Forum on Specifications and Design Languages, FDL 2012
Y2 - 1 September 2012 through 1 September 2012
ER -